66 lines
2.8 KiB
Verilog
66 lines
2.8 KiB
Verilog
// Sha3Accel w/ a blackbox (a dummy DCO) included inside
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module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2]
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input clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4]
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input reset, // @[:example.TestHarness.Sha3RocketConfig.fir@135907.4]
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output io_cmd_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input io_cmd_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input [6:0] io_cmd_bits_inst_funct, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input [63:0] io_cmd_bits_rs1, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input [63:0] io_cmd_bits_rs2, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input io_mem_req_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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output io_mem_req_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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output [39:0] io_mem_req_bits_addr, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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output [7:0] io_mem_req_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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output [4:0] io_mem_req_bits_cmd, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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output [63:0] io_mem_req_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input io_mem_resp_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input [7:0] io_mem_resp_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input [63:0] io_mem_resp_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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output io_busy, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
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input [13:0] col_sel_b,
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input [15:0] row_sel_b,
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input [7:0] code_regulator,
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input dither,
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input sleep_b,
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output dco_clock
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);
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Sha3Accel sha3 (
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.clock(clock),
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.reset(reset),
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.io_cmd_ready(io_cmd_ready),
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.io_cmd_valid(io_cmd_valid),
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.io_cmd_bits_inst_funct(io_cmd_bits_inst_funct),
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.io_cmd_bits_rs1(io_cmd_bits_rs1),
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.io_cmd_bits_rs2(io_cmd_bits_rs2),
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.io_mem_req_ready(io_mem_req_ready),
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.io_mem_req_valid(io_mem_req_valid),
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.io_mem_req_bits_addr(io_mem_req_bits_addr),
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.io_mem_req_bits_tag(io_mem_req_bits_tag),
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.io_mem_req_bits_cmd(io_mem_req_bits_cmd),
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.io_mem_req_bits_data(io_mem_req_bits_data),
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.io_mem_resp_valid(io_mem_resp_valid),
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.io_mem_resp_bits_tag(io_mem_resp_bits_tag),
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.io_mem_resp_bits_data(io_mem_resp_bits_data),
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.io_busy(io_busy)
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);
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ExampleDCO dco (
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.col_sel_b(col_sel_b),
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.row_sel_b(row_sel_b),
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.code_regulator(code_regulator),
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.dither(dither),
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.sleep_b(sleep_b),
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.clock(dco_clock)
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);
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endmodule
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module ExampleDCO (
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input [13:0] col_sel_b,
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input [15:0] row_sel_b,
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input [7:0] code_regulator,
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input dither,
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input sleep_b,
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output clock
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);
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endmodule
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