d06abdb419
**Related issue**: N/A
**Type of change**: bug fix
**Impact**: other
**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](d4b3878e4f/xilinx/common/tcl/prologue.tcl)
Swaping the two arguments can resolve bug.
144 lines
4.9 KiB
Makefile
144 lines
4.9 KiB
Makefile
#########################################################################################
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# fpga prototype makefile
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#########################################################################################
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#########################################################################################
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# general path variables
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#########################################################################################
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base_dir=$(abspath ..)
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sim_dir=$(abspath .)
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# do not generate simulation files
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sim_name := none
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#########################################################################################
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# include shared variables
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#########################################################################################
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SUB_PROJECT ?= vcu118
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ifeq ($(SUB_PROJECT),vcu118)
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SBT_PROJECT ?= fpga_platforms
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MODEL ?= VCU118FPGATestHarness
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VLOG_MODEL ?= VCU118FPGATestHarness
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MODEL_PACKAGE ?= chipyard.fpga.vcu118
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CONFIG ?= RocketVCU118Config
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CONFIG_PACKAGE ?= chipyard.fpga.vcu118
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GENERATOR_PACKAGE ?= chipyard
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TB ?= none # unused
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TOP ?= ChipTop
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BOARD ?= vcu118
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FPGA_BRAND ?= xilinx
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endif
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ifeq ($(SUB_PROJECT),bringup)
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SBT_PROJECT ?= fpga_platforms
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MODEL ?= BringupVCU118FPGATestHarness
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VLOG_MODEL ?= BringupVCU118FPGATestHarness
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MODEL_PACKAGE ?= chipyard.fpga.vcu118.bringup
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CONFIG ?= RocketBringupConfig
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CONFIG_PACKAGE ?= chipyard.fpga.vcu118.bringup
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GENERATOR_PACKAGE ?= chipyard
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TB ?= none # unused
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TOP ?= ChipTop
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BOARD ?= vcu118
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FPGA_BRAND ?= xilinx
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endif
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ifeq ($(SUB_PROJECT),arty)
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# TODO: Fix with Arty
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SBT_PROJECT ?= fpga_platforms
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MODEL ?= ArtyFPGATestHarness
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VLOG_MODEL ?= ArtyFPGATestHarness
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MODEL_PACKAGE ?= chipyard.fpga.arty
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CONFIG ?= TinyRocketArtyConfig
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CONFIG_PACKAGE ?= chipyard.fpga.arty
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GENERATOR_PACKAGE ?= chipyard
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TB ?= none # unused
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TOP ?= ChipTop
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BOARD ?= arty
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FPGA_BRAND ?= xilinx
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endif
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include $(base_dir)/variables.mk
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# default variables to build the arty example
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# setup the board to use
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.PHONY: default
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default: $(mcs)
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#########################################################################################
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# misc. directories
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#########################################################################################
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fpga_dir := $(base_dir)/fpga/fpga-shells/$(FPGA_BRAND)
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fpga_common_script_dir := $(fpga_dir)/common/tcl
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#########################################################################################
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# setup misc. sim files
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#########################################################################################
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SIM_FILE_REQS += \
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$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v
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# copy files but ignore *.h files in *.f (match vcs)
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$(sim_files): $(SIM_FILE_REQS) | $(build_dir)
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cp -f $^ $(build_dir)
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$(foreach file,\
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$^,\
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$(if $(filter %.h,$(file)),\
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,\
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echo "$(addprefix $(build_dir)/, $(notdir $(file)))" >> $@;))
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#########################################################################################
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# import other necessary rules and variables
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#########################################################################################
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include $(base_dir)/common.mk
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#########################################################################################
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# copy from other directory
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#########################################################################################
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all_vsrcs := \
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$(sim_vsrcs) \
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$(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v \
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$(fpga_dir)/common/vsrc/PowerOnResetFPGAOnly.v
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#########################################################################################
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# vivado rules
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#########################################################################################
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# combine all sources into single .f
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synth_list_f := $(build_dir)/$(long_name).vsrcs.f
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$(synth_list_f): $(sim_common_files) $(all_vsrcs)
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$(foreach file,$(all_vsrcs),echo "$(file)" >> $@;)
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cat $(sim_common_files) >> $@
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BIT_FILE := $(build_dir)/obj/$(MODEL).bit
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$(BIT_FILE): $(synth_list_f)
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cd $(build_dir); vivado \
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-nojournal -mode batch \
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-source $(fpga_common_script_dir)/vivado.tcl \
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-tclargs \
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-top-module "$(MODEL)" \
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-F "$(synth_list_f)" \
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-board "$(BOARD)" \
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-ip-vivado-tcls "$(shell find '$(build_dir)' -name '*.vivado.tcl')"
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.PHONY: bitstream
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bitstream: $(BIT_FILE)
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.PHONY: debug-bitstream
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debug-bitstream: $(build_dir)/obj/post_synth.dcp
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cd $(build_dir); vivado \
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-nojournal -mode batch \
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-source $(sim_dir)/scripts/run_impl_bitstream.tcl \
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-tclargs \
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$(build_dir)/obj/post_synth.dcp \
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$(BOARD) \
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$(build_dir)/debug_obj \
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$(fpga_common_script_dir)
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#########################################################################################
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# general cleanup rules
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#########################################################################################
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.PHONY: clean
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clean:
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rm -rf $(gen_dir)
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