Jerry Zhao 4cdc2801be Override spike's misa in cosim mode ...

Writable bits in MISA is implementation-defined, so we can't follow spike here.

2023-02-22 15:15:28 -08:00

..

boom @ deae9f7046

Bump boom

2023-02-22 00:21:44 -08:00

chipyard/src

Override spike's misa in cosim mode

2023-02-22 15:15:28 -08:00

constellation @ 4606ee19b7

Bump constellation for some bug fixes

2023-02-11 12:32:17 -08:00

cva6 @ 737fd83b82

Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

2023-01-26 00:12:28 -08:00

fft-generator @ a31bd038dd

Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

2023-01-26 00:12:28 -08:00

firechip/src/main/scala

Remove Ringbus config from firechip

2023-02-11 15:48:16 -08:00

gemmini @ b6389f3ea7

Bump gemmini

2023-02-05 09:59:58 -08:00

hwacha @ e1be8e2a41

Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

2023-01-26 00:12:28 -08:00

ibex @ 5a512227d8

Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

2023-01-26 00:12:28 -08:00

icenet @ fb23840eab

Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

2023-01-26 00:12:28 -08:00

mempress @ b9eaedc061

bump mempress

2023-01-05 22:24:16 -08:00

nvdla @ 2b17011b26

Bump to master commits

2022-02-10 17:24:54 -08:00

riscv-sodor @ d6ccc5de5c

Bump sodor for SLLI/SRLI/SRAI fix

2023-02-10 16:11:04 -08:00

rocket-chip @ f5ebf26b36

Bump rocket-chip

2023-02-14 00:35:30 -08:00

sha3 @ 98089ba372

Bump to scala 2.13.10/chisel 3.5.5/latest rocketchip

2023-01-26 00:12:28 -08:00

sifive-blocks @ 4273925fdd

Bump rocket-chip components

2023-02-01 14:54:16 -08:00

sifive-cache @ 850e12154c

Bump rocket-chip components

2023-02-01 14:54:16 -08:00

testchipip @ 2906d503cf

Bump testchipip

2023-01-29 16:31:13 -08:00

tracegen

Move boom's tracegen interface to boom submodule - this improves maintainability

2023-02-08 09:35:13 -08:00