wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
5966588d6812e001d2810ad99b4b6fb27985d094
chipyard/generators
History
Jerry Zhao 5966588d68 Merge pull request #790 from ucb-bar/simdram_timings 
Passing MBus clock frequency to SimDRAM
2021-02-17 23:10:51 -08:00
..
boom @ e1a70afed7
bump boom along same PR
2020-12-23 15:00:57 +00:00
chipyard/src
Merge pull request #790 from ucb-bar/simdram_timings
2021-02-17 23:10:51 -08:00
cva6 @ 139741a584
Bump cva6 for ucb-bar/cva6-wrapper#11
2020-12-18 20:54:31 +00:00
firechip/src
WithFireSimFAME5 to allow non Rocket/BOOM build
2021-02-01 17:33:07 -08:00
gemmini @ e6e14f7117
Bump BOOM/Gemmini
2020-12-11 14:20:09 -08:00
hwacha @ 62c01f5a88
Bump hwacha for ucb-bar/hwacha#24
2020-12-18 20:52:00 +00:00
icenet @ 084ca50706
Bump icenet
2020-12-10 06:34:39 +00:00
nvdla @ b2b78c9f89
NVDLA Integration + Cleanup Ariane Preprocessing (#505)
2020-05-16 12:22:30 -07:00
riscv-sodor @ 449354c27b
Bump testchipip and sodor | increase sodor SerialTL width for faster binary loading
2021-01-10 23:39:16 -08:00
rocket-chip @ a7b016e46e
Start RC bump
2020-12-18 18:00:21 +00:00
sha3 @ 74e41f5792
Attempt at "fixing" build.sbt | Bump sub-projects
2020-11-30 21:22:55 -08:00
sifive-blocks @ 545a396f34
Bump sifive-blocks
2021-01-08 10:56:30 -08:00
sifive-cache @ e3a3000cc1
bump sifive-cache for merged sifive/block-inclusivecache-sifive#15
2020-12-21 18:15:49 +00:00
testchipip @ f27055929a
Passing MBus clock frequency to SimDRAM
2021-02-08 02:11:18 -08:00
tracegen
update parameter classes for RC additions
2020-12-18 23:24:19 +00:00
utilities/src/main
Fix TLMemPort comment | Use Option instead of NoSimulator
2020-11-15 15:44:38 -08:00