169 lines
8.9 KiB
ReStructuredText
169 lines
8.9 KiB
ReStructuredText
.. _chip-communication:
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Communicating with the DUT
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===============================
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There are two types of DUTs that can be made: `tethered` or `standalone` DUTs.
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A `tethered` DUT is where a host computer (or just host) must send transactions to the DUT to bringup a program.
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This differs from a `standalone` DUT that can bringup itself (has its own bootrom, loads programs itself, etc).
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An example of a tethered DUT is a Chipyard simulation where the host loads the test program into the DUTs memory and signals to the DUT that the program is ready to run.
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An example of a standalone DUT is a Chipyard simulation where a program can be loaded from an SDCard by default.
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In this section, we mainly describe how to communicate to tethered DUTs.
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There are two ways the host (otherwise known as the outside world) can communicate with a tethered Chipyard DUT:
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* Using the Tethered Serial Interface (TSI) or the Debug Module Interface (DMI) with the Front-End Server (FESVR) to communicate with the DUT
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* Using the JTAG interface with OpenOCD and GDB to communicate with the DUT
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The following picture shows a block diagram view of all the supported communication mechanisms
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split between the host and the simulation.
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.. image:: ../_static/images/chip-communication.png
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Using the Tethered Serial Interface (TSI) or the Debug Module Interface (DMI)
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-----------------------------------------------------------------------------
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If you are using TSI or DMI to communicate with the DUT, you are using
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the Front-End Server (FESVR) to facilitate communication between the host and the DUT.
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Primer on the Front-End Server (FESVR)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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FESVR is a C++ library that manages communication
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between a host machine and a RISC-V DUT. For debugging, it provides a simple API to reset,
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send messages, and load/run programs on a DUT. It also emulates peripheral devices.
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It can be incorporated with simulators (VCS, Verilator, FireSim), or used in a bringup sequence
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for a taped out chip.
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Specifically, FESVR uses the Host Target Interface (HTIF), a communication protocol,
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to speak with the DUT. HTIF is a non-standard Berkeley protocol that uses a FIFO non-blocking
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interface to communicate with the DUT. It defines a protocol where you can read/write memory,
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load/start/stop the program, and more. Both TSI and DMI implement this HTIF protocol differently
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in order to communicate with the DUT.
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Using the Tethered Serial Interface (TSI)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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By default, Chipyard uses the Tethered Serial Interface (TSI) to communicate with the DUT.
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TSI protocol is an implementation of HTIF that is used to send commands to the
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RISC-V DUT. These TSI commands are simple R/W commands
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that are able to probe the DUT's memory space. During simulation, the host sends TSI commands to a
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simulation stub called ``SimSerial`` (C++ class) that resides in a ``SimSerial`` verilog module
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(both are located in the ``generators/testchipip`` project). This ``SimSerial`` verilog module then
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sends the TSI command recieved by the simulation stub into the DUT which then converts the TSI
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command into a TileLink request. This conversion is done by the ``SerialAdapter`` module
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(located in the ``generators/testchipip`` project). In simulation, FESVR
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resets the DUT, writes into memory the test program, and indicates to the DUT to start the program
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through an interrupt (see :ref:`Chipyard Boot Process`). Using TSI is currently the fastest
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mechanism to communicate with the DUT in simulation.
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In the case of a chip tapeout bringup, TSI commands can be sent over a custom communication
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medium to communicate with the chip. For example, some Berkeley tapeouts have a FPGA
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with a RISC-V soft-core that runs FESVR. The FESVR on the soft-core sends TSI commands
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to a TSI-to-TileLink converter living on the FPGA (i.e. ``SerialAdapter``). Then this converter
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sends the converted TileLink commands over a serial link to the chip. The following image shows this flow:
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.. image:: ../_static/images/chip-bringup.png
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Using the Debug Module Interface (DMI)
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Another option to interface with the DUT is to use the Debug Module Interface (DMI).
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Similar to TSI, the DMI protocol is an implementation of HTIF.
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In order to communicate with the DUT with the DMI protocol, the DUT needs to contain a Debug Transfer Module (DTM).
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The DTM is given in the `RISC-V Debug Specification <https://riscv.org/specifications/debug-specification/>`__
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and is responsible for managing communication between the DUT and whatever lives on the other side of the DMI (in this case FESVR).
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This is implemented in the Rocket Chip ``Subsystem`` by having the ``HasPeripheryDebug`` and ``HasPeripheryDebugModuleImp`` mixins.
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During simulation, the host sends DMI commands to a
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simulation stub called ``SimDTM`` (C++ class) that resides in a ``SimDTM`` verilog module
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(both are located in the ``generators/rocket-chip`` project). This ``SimDTM`` verilog module then
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sends the DMI command recieved by the simulation stub into the DUT which then converts the DMI
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command into a TileLink request. This conversion is done by the DTM named ``DebugModule`` in the ``generators/rocket-chip`` project.
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When the DTM receives the program to load, it starts to write the binary byte-wise into memory.
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This is considerably slower than the TSI protocol communication pipeline (i.e. ``SimSerial``/``SerialAdapter``/TileLink)
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which directly writes the program binary to memory.
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Thus, Chipyard removes the DTM by default in favor of the TSI protocol for DUT communication.
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Starting the TSI or DMI Simulation
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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All default Chipyard configurations use TSI to communicate between the simulation and the simulated SoC/DUT. Hence, when running a
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software RTL simulation, as is indicated in the :ref:`Software RTL Simulation` section, you are in-fact using TSI to communicate with the DUT. As a
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reminder, to run a software RTL simulation, run:
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.. code-block:: bash
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cd sims/verilator
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# or
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cd sims/vcs
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make CONFIG=LargeBoomConfig run-asm-tests
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FireSim FPGA-accelerated simulations use TSI by default as well.
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If you would like to build and simulate a Chipyard configuration with a DTM configured for DMI communication, then you must create a
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top-level system with the DTM (``TopWithDTM``), a test-harness to connect to the DTM (``TestHarnessWithDTM``), as well as a config to use that top-level system.
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.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
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:language: scala
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:start-after: DOC include start: DmiRocket
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:end-before: DOC include end: DmiRocket
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In this example, the ``WithDTMTop`` mixin specifies that the top-level SoC will instantiate a DTM (that by default is setup to use DMI).
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The rest of the mixins specify the rest of the system (cores, accelerators, etc).
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Then you can run simulations with the new DMI-enabled top-level and test-harness.
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.. code-block:: bash
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cd sims/verilator
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# or
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cd sims/vcs
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make CONFIG=dmiRocketConfig TOP=TopWithDTM MODEL=TestHarnessWithDTM run-asm-tests
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Using the JTAG Interface
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------------------------
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The main way to use JTAG with a Rocket Chip based system is to instantiate the Debug Transfer Module (DTM)
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and configure it to use a JTAG interface (by default the DTM is setup to use the DMI interface mentioned above).
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Creating a DTM+JTAG Config
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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First, a DTM config must be created for the system that you want to create.
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This step is similar to the DMI simulation section within the :ref:`Starting the TSI or DMI Simulation` section.
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First, you must make a top-level system (``TopWithDTM``) and test-harness (``TestHarnessWithDTM``) that instantiates
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and connects the DTM correctly. The configuration is very similar to a DMI-based configuration. The main difference
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is the addition of the ``WithJtagDTM`` mixin that configures the instantiated DTM to use the JTAG protocol as the
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bringup method.
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.. literalinclude:: ../../generators/example/src/main/scala/RocketConfigs.scala
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:language: scala
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:start-after: DOC include start: JtagRocket
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:end-before: DOC include end: JtagRocket
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Building a DTM+JTAG Simulator
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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After creating the config, call the ``make`` command like the following to build a simulator for your RTL:
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.. code-block:: bash
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cd sims/verilator
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# or
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cd sims/vcs
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make CONFIG=jtagRocketConfig TOP=TopWithDTM MODEL=TestHarnessWithDTM
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In this example, the simulation will use the config that you previously specified, as well as set
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the other parameters that are needed to satisfy the build system. After that point, you
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should have a JTAG enabled simulator that you can attach to using OpenOCD and GDB!
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Debugging with JTAG
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Please refer to the following resources on how to debug with JTAG.
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* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb
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* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb
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