46 lines
1.6 KiB
Scala
46 lines
1.6 KiB
Scala
package chipyard.fpga.vcu118
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import chisel3._
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import chisel3.experimental.{BaseModule}
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import freechips.rocketchip.util.{HeterogeneousBag}
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import freechips.rocketchip.tilelink.{TLBundle}
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import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
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import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
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import chipyard.{HasHarnessSignalReferences, CanHaveMasterTLMemPort}
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import chipyard.harness.{OverrideHarnessBinder}
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/*** UART ***/
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class WithUART extends OverrideHarnessBinder({
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(system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
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th match { case vcu118th: VCU118FPGATestHarnessImp => {
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vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head
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} }
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}
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})
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/*** SPI ***/
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class WithSPISDCard extends OverrideHarnessBinder({
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(system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
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th match { case vcu118th: VCU118FPGATestHarnessImp => {
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vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head
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} }
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}
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})
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/*** Experimental DDR ***/
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class WithDDRMem extends OverrideHarnessBinder({
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(system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
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th match { case vcu118th: VCU118FPGATestHarnessImp => {
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require(ports.size == 1)
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val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1)
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val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
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bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
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ddrClientBundle <> ports.head
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} }
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}
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})
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