101 lines
4.8 KiB
ReStructuredText
101 lines
4.8 KiB
ReStructuredText
.. _advanced-usage:
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Advanced Usage
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==============
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Hammer Development
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------------------
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If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
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.. code-block:: shell
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pip install -e <path/to/hammer>
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Alternative RTL Flows
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---------------------
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The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).
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.. code-block:: shell
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CUSTOM_VLOG=<your Verilog files>
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VLSI_TOP=<your top module>
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``CUSTOM_VLOG`` breaks the dependency on the rest of the Chipyard infrastructure and does not start any Chisel/FIRRTL elaboration. ``VLSI_TOP`` selects the top module from your custom Verilog files.
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Under the Hood
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--------------
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To uncover what is happening under the hood, here are the commands that are executed:
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For ``make syn``:
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.. code-block:: shell
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./example-vlsi -e /path/to/env.yml -p /path/to/example.yml -p /path/to/inputs.yml --obj_dir /path/to/build syn
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``example-vlsi`` is the entry script as explained before, ``-e`` provides the environment yml, ``-p`` points to configuration yml/jsons, ``--obj_dir`` speficies the destination directory, and ``syn`` is the action.
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For ``make par``:
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.. code-block:: shell
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./example-vlsi -e /path/to/env.yml -p /path/to/syn-output-full.json -o /path/to/par-input.json --obj_dir /path/to/build syn-to-par
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./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json --obj_dir /path/to/build par
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A ``syn-to-par`` action translates the synthesis output configuration into an input configuration given by ``-o``. Then, this is passed to the ``par`` action.
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For more information about all the options that can be passed to the Hammer command-line driver, please see the Hammer documentation.
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Manual Step Execution & Dependency Tracking
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-------------------------------------------
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It is invariably necessary to debug certain steps of the flow, e.g. if the power strap settings need to be updated. The underlying Hammer commands support options such as ``--stop_after_step``, ``--start_before_step``, and ``--only_step``. These allow you to control which steps of a particular action are executed.
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Make's dependency tracking can sometimes result in re-starting the entire flow when the user only wants to re-run a certain action. Hammer's build system has "redo" targets such as ``redo-syn`` and ``redo-par`` to run certain actions without typing out the entire Hammer command.
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Say you need to update some power straps settings in ``new_power_straps.yml`` and want to try out the new settings:
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.. code-block:: shell
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make redo-par HAMMER_REDO_ARGS='-p new_power_straps.yml --only_step power_straps'
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The command that is executed will be:
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.. code-block:: shell
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./example-vlsi -e /path/to/env.yml -p /path/to/par-input.json -p new_power_straps.yml --only_step power_straps --obj_dir /path/to/build par
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Hierarchical RTL/Gate-level Simulation, Power Estimation
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--------------------------------------------------------
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With the Synopsys plugin, hierarchical RTL and gate-level simulation is supported using VCS at the chip-level. Also, rtl-level/post-syn power estimation with Joules and post-par power estimation with Voltus in the Cadence plugin is also supported. Special Make targets are provided in the ``vlsi/`` directory in ``sims.mk`` and ``power.mk``. Here is a brief description:
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* ``sim-rtl``: RTL-level simulation
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* ``sim-rtl-debug``: Also write a FSDB waveform
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* ``sim-syn``: Post-synthesis gate-level simulation
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* ``sim-syn-debug``: Also write a FSDB waveform
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* ``sim-syn-timing-debug``: Timing-annotated with FSDB waveform
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* ``sim-par``: Post-par gate-level simulation
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* ``sim-par-debug``: Also write a FSDB waveform
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* ``sim-par-timing-debug``: Timing-annotated with FSDB waveform
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* ``power-rtl``: RTL-level power estimation
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* Note: this will run ``sim-rtl-debug`` first
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* ``power-syn``: Post-synthesis power estimation
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* Note: this will run ``sim-syn-debug`` first
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* ``power-par``: Post-par power estimation
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* Note: this will run ``sim-par-debug`` first
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* ``redo-`` can be appended to all above targets to break dependency tracking, like described above.
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* ``-$(VLSI_TOP)`` suffixes denote simulations/power analysis on a submodule in a hierarchical flow (remember to override this variable). Note that you must provide the testbenches for these modules since the default testbench only simulates a Chipyard-based ``ChipTop`` DUT instance.
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The simulation configuration (e.g. binaries) can be edited for your design. See the ``Makefile`` and refer to Hammer's documentation for how to set up simulation parameters for your design.
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