Files
chipyard/verisim/Makefile
2016-10-25 11:38:00 -07:00

53 lines
1.6 KiB
Makefile

base_dir=$(abspath ..)
sim_dir=$(abspath .)
PROJECT ?= example
MODEL ?= TestHarness
CONFIG ?= DefaultExampleConfig
CFG_PROJECT ?= $(PROJECT)
TB ?= TestDriver
sim = simulator-$(PROJECT)-$(CONFIG)
sim_debug = simulator-$(PROJECT)-$(CONFIG)-debug
default: $(sim)
debug: $(sim_debug)
CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include
LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
include $(base_dir)/Makefrag
include $(sim_dir)/Makefrag-verilator
long_name = $(PROJECT).$(MODEL).$(CONFIG)
sim_vsrcs = \
$(build_dir)/$(long_name).v \
$(base_dir)/testchipip/vsrc/SimSerial.v
sim_csrcs = \
$(base_dir)/testchipip/csrc/SimSerial.cc \
$(base_dir)/testchipip/csrc/verilator-harness.cc
model_dir = $(build_dir)/$(long_name)
model_dir_debug = $(build_dir)/$(long_name).debug
model_header = $(model_dir)/V$(MODEL).h
model_header_debug = $(model_dir_debug)/V$(MODEL).h
$(sim): $(sim_vsrcs) $(sim_csrcs) $(INSTALLED_VERILATOR)
mkdir -p $(build_dir)/$(long_name)
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-o $(sim_dir)/$@ $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(MODEL).mk
$(sim_debug): $(sim_vsrcs) $(sim_csrcs) $(INSTALLED_VERILATOR)
mkdir -p $(build_dir)/$(long_name).debug
$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-o $(sim_dir)/$@ $< $(sim_csrcs) -LDFLAGS "$(LDFLAGS)" \
-CFLAGS "-I$(build_dir) -include $(model_header_debug)"
$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(MODEL).mk