107 lines
3.8 KiB
Scala
107 lines
3.8 KiB
Scala
//See LICENSE for license details.
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package firesim.firesim
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import chisel3._
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import chisel3.experimental.annotate
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import freechips.rocketchip.config.{Field, Config, Parameters}
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import freechips.rocketchip.diplomacy.{LazyModule}
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import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
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import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
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import freechips.rocketchip.tile.{RocketTile}
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import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
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import testchipip.{CanHavePeripherySerialModuleImp, CanHavePeripheryBlockDeviceModuleImp, CanHaveTraceIOModuleImp}
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import icenet.CanHavePeripheryIceNICModuleImp
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import junctions.{NastiKey, NastiParameters}
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import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
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import midas.targetutils.{MemModelAnnotation}
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import firesim.bridges._
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import firesim.configs.MemModelKey
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import tracegen.HasTraceGenTilesModuleImp
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import boom.common.{BoomTile}
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import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
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import chipyard.HasBoomAndRocketTilesModuleImp
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class WithSerialBridge extends OverrideIOBinder({
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(c, r, s, target: CanHavePeripherySerialModuleImp) => target.serial.map(s => SerialBridge(s)(target.p)).toSeq
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})
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class WithNICBridge extends OverrideIOBinder({
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(c, r, s, target: CanHavePeripheryIceNICModuleImp) => target.net.map(n => NICBridge(n)(target.p)).toSeq
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})
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class WithUARTBridge extends OverrideIOBinder({
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(c, r, s, target: HasPeripheryUARTModuleImp) => target.uart.map(u => UARTBridge(u)(target.p)).toSeq
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})
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class WithBlockDeviceBridge extends OverrideIOBinder({
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(c, r, s, target: CanHavePeripheryBlockDeviceModuleImp) => target.bdev.map(b => BlockDevBridge(b, target.reset.toBool)(target.p)).toSeq
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})
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class WithFASEDBridge extends OverrideIOBinder({
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(c, r, s, t: CanHaveMasterAXI4MemPortModuleImp) => {
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implicit val p = t.p
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(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
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(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
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val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
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axi4Bundle.ar.bits.addr.getWidth,
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axi4Bundle.ar.bits.id.getWidth)
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FASEDBridge(axi4Bundle, t.reset.toBool,
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CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
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})
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}).toSeq
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}
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})
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class WithTracerVBridge extends OverrideIOBinder({
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(c, r, s, target: CanHaveTraceIOModuleImp) => target.traceIO.map(t => TracerVBridge(t)(target.p)).toSeq
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})
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class WithTraceGenBridge extends OverrideIOBinder({
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(c, r, s, target: HasTraceGenTilesModuleImp) => Seq(GroundTestBridge(target.success)(target.p))
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})
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class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
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(c, r, s, target: HasBoomAndRocketTilesModuleImp) => {
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target.outer.tiles.map {
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case r: RocketTile => {
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annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
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r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
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}
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case b: BoomTile => {
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val core = b.module.core
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core.iregfile match {
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case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
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case _ => Nil
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}
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if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
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case frf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(frf.regfile))
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case _ => Nil
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}
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}
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}
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Nil
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}
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})
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// Shorthand to register all of the provided bridges above
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class WithDefaultFireSimBridges extends Config(
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new chipyard.iobinders.WithGPIOTiedOff ++
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new chipyard.iobinders.WithTiedOffDebug ++
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new chipyard.iobinders.WithTieOffInterrupts ++
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new WithSerialBridge ++
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new WithNICBridge ++
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new WithUARTBridge ++
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new WithBlockDeviceBridge ++
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new WithFASEDBridge ++
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new WithFireSimMultiCycleRegfile ++
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new WithTracerVBridge
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)
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