61 lines
4.3 KiB
ReStructuredText
61 lines
4.3 KiB
ReStructuredText
Running a Design on VCU118
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==========================
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Basic VCU118 Design
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-------------------
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The default Xilinx VCU118 harness is setup to have UART, a SPI SDCard, and DDR backing memory.
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This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118).
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To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``.
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Adding this config fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config.
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.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala
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:language: scala
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:start-after: DOC include start: AbstractVCU118 and Rocket
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:end-before: DOC include end: AbstractVCU118 and Rocket
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Brief Implementation Description + More Complicated Designs
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-----------------------------------------------------------
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The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design.
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This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target.
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The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs.
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Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral.
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For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``.
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.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala
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:language: scala
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:start-after: DOC include start: UartOverlay
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:end-before: DOC include end: UartOverlay
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Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART.
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The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``.
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Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope).
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This pattern is similar for all other ``Overlays`` in the test harness.
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They must be "placed" and given a set of inputs (IOs, parameters).
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The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA.
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.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala
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:language: scala
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:start-after: DOC include start: ClockOverlay
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:end-before: DOC include end: ClockOverlay
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Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``.
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For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design.
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After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs.
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This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``).
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For more information on harness binders and io binders, refer to :ref:`Customization/IOBinders:IOBinders and HarnessBinders`.
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Introduction to the Bringup Platform
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------------------------------------
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An example of a more complicated design used for Chipyard test chips can be viewed in ``fpga/src/main/scala/vcu118/bringup/``.
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This example extends the default test harness and creates new ``Overlays`` to connect to a DUT (connected to the FMC port).
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Extensions include another UART (connected over FMC), I2C (connected over FMC), miscellaneous GPIOS (can be connected to anything), and a TSI Host Widget.
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The TSI Host Widget is used to interact with the DUT from the prototype over a SerDes link (sometimes called the Low BandWidth InterFace - LBWIF) and provide access to a channel of the FPGA's DRAM.
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.. Note:: Remember that since whenever a new test harness is created (or the config changes, or the config packages changes, or...), you need to modify the make invocation.
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For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bitstream``.
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See :ref:`Prototyping/General:Generating a Bitstream` for information on the various make variables.
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