190 lines
9.9 KiB
Makefile
190 lines
9.9 KiB
Makefile
#########################################################################################
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# set default shell for make
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#########################################################################################
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SHELL=/bin/bash
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#########################################################################################
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# extra make variables/rules from subprojects
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#
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# EXTRA_GENERATOR_REQS - requirements needed for the main generator
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# EXTRA_SIM_FLAGS - runtime simulation flags
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# EXTRA_SIM_CC_FLAGS - cc flags for simulators
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# EXTRA_SIM_SOURCES - simulation sources needed for simulator
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# EXTRA_SIM_REQS - requirements to build the simulator
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#########################################################################################
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include $(base_dir)/generators/ariane/ariane.mk
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include $(base_dir)/generators/tracegen/tracegen.mk
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#########################################################################################
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# Prerequisite lists
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#########################################################################################
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# Returns a list of files in directory $1 with file extension $2.
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lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null)
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SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell)
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SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala)
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VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v)
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#########################################################################################
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# rocket and testchipip classes
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#########################################################################################
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# NB: target/ lives under source ----V , due to how we're handling midas dependency injection
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ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/src/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
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TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes"
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#########################################################################################
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# jar creation variables and rules
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#########################################################################################
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FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
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FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar
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$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
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$(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala
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mkdir -p $(@D)
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cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@
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touch $@
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$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
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cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly"
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mkdir -p $(@D)
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cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@
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touch $@
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#########################################################################################
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# create list of simulation file inputs
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#########################################################################################
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$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR)
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cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
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#########################################################################################
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# create firrtl file rule and variables
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#########################################################################################
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.INTERMEDIATE: generator_temp
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$(FIRRTL_FILE) $(ANNO_FILE): generator_temp
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@echo "" > /dev/null
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# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
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generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS)
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mkdir -p $(build_dir)
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cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator \
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--target-dir $(build_dir) \
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--name $(long_name) \
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--top-module $(MODEL_PACKAGE).$(MODEL) \
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--legacy-configs $(CONFIG_PACKAGE).$(CONFIG)"
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.PHONY: firrtl
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firrtl: $(FIRRTL_FILE)
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#########################################################################################
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# create verilog files rules and variables
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#########################################################################################
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REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF)
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HARNESS_CONF_FLAGS = -thconf $(HARNESS_SMEMS_CONF)
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TOP_TARGETS = $(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes)
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HARNESS_TARGETS = $(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes)
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# DOC include start: FirrtlCompiler
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# NOTE: These *_temp intermediate targets will get removed in favor of make 4.3 grouped targets (&: operator)
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.INTERMEDIATE: firrtl_temp
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$(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp
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@echo "" > /dev/null
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firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
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cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" && touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
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# DOC include end: FirrtlCompiler
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# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
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MACROCOMPILER_MODE ?= --mode synflops
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.INTERMEDIATE: top_macro_temp
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$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): top_macro_temp
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@echo "" > /dev/null
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top_macro_temp: $(TOP_SMEMS_CONF)
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cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)"
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HARNESS_MACROCOMPILER_MODE = --mode synflops
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.INTERMEDIATE: harness_macro_temp
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$(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): harness_macro_temp
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@echo "" > /dev/null
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harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp
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cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"
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########################################################################################
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# remove duplicate files and headers in list of simulation file inputs
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########################################################################################
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$(sim_common_files): $(sim_files) $(sim_top_blackboxes) $(sim_harness_blackboxes)
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awk '{print $1;}' $^ | sort -u | grep -v '.*\.\(svh\|h\)$$' > $@
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#########################################################################################
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# helper rule to just make verilog files
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#########################################################################################
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.PHONY: verilog
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verilog: $(sim_vsrcs)
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#########################################################################################
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# helper rules to run simulations
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#########################################################################################
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.PHONY: run-binary run-binary-fast run-binary-debug run-fast
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run-binary: $(sim)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
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#########################################################################################
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# helper rules to run simulator as fast as possible
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#########################################################################################
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run-binary-fast: $(sim)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $(BINARY) </dev/null | tee $(sim_out_name).log)
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#########################################################################################
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# helper rules to run simulator with as much debug info as possible
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#########################################################################################
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run-binary-debug: $(sim_debug)
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(set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(WAVEFORM_FLAG) $(PERMISSIVE_OFF) $(BINARY) </dev/null 2> >(spike-dasm > $(sim_out_name).out) | tee $(sim_out_name).log)
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run-fast: run-asm-tests-fast run-bmark-tests-fast
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run-none: $(output_dir)/none.out
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run-none-fast: $(output_dir)/none.run
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run-none-debug: $(output_dir)/none.vpd
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#########################################################################################
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# run assembly/benchmarks rules
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#########################################################################################
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$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
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mkdir -p $(output_dir)
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ln -sf $< $@
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$(output_dir)/%.run: $(output_dir)/% $(sim)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
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$(output_dir)/%.out: $(output_dir)/% $(sim)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) $< </dev/null 2> >(spike-dasm > $@) | tee $<.log)
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$(output_dir)/none.run: $(sim)
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mkdir -p $(output_dir)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(PERMISSIVE_OFF) $< </dev/null | tee $<.log) && touch $@
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$(output_dir)/none.out: $(sim)
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mkdir -p $(output_dir)
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(set -o pipefail && $(sim) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(VERBOSE_FLAGS) $(PERMISSIVE_OFF) none </dev/null 2> >(spike-dasm > $@) | tee $(output_dir)/none.log)
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#########################################################################################
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# include build/project specific makefrags made from the generator
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#########################################################################################
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ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
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-include $(build_dir)/$(long_name).d
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endif
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#######################################
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# Rules for building DRAMSim2 library #
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#######################################
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dramsim_dir = $(base_dir)/tools/DRAMSim2
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dramsim_lib = $(dramsim_dir)/libdramsim.a
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$(dramsim_lib):
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$(MAKE) -C $(dramsim_dir) $(notdir $@)
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