dunn 7d1a1539e6 Initial pass at HarnessBinders for Arty.

2020-10-09 23:17:36 -07:00

..

fpga-shells @ e8e7f8a321

First draft of local FPGA support, targeting ARTY. Able to build verilog and bitfile for Rocket + Chipyard GCD example. To test, add GCD mixin to fpga/src/main/scala/arty/Config.scala, run make -f Makefile.e300artydevkit verilog and make -f Makefile.e300artydevkit mcs in fpga directory. Output will be in fpga/build.

2020-09-02 12:48:44 -07:00

src/main/scala/arty

Initial pass at HarnessBinders for Arty.

2020-10-09 23:17:36 -07:00

.gitignore

Delete old makefiles | Full switch to CY make system

2020-09-03 21:28:05 -07:00

Makefile

Small cleanup to CY DigitalTop | Move E300 configs to unique folder

2020-09-07 15:26:30 -07:00