95 lines
4.6 KiB
ReStructuredText
95 lines
4.6 KiB
ReStructuredText
Test Chip IP
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============
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Chipyard includes a Test Chip IP library which provides various hardware
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widgets that may be useful when designing SoCs. This includes a :ref:`Generators/TestChipIP:Serial Adapter`,
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:ref:`Generators/TestChipIP:Block Device Controller`, :ref:`Generators/TestChipIP:TileLink SERDES`, :ref:`Generators/TestChipIP:TileLink Switcher`,
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:ref:`Generators/TestChipIP:TileLink Ring Network`, and :ref:`Generators/TestChipIP:UART Adapter`.
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Serial Adapter
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--------------
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The serial adapter is used by tethered test chips to communicate with the host
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processor. An instance of RISC-V frontend server running on the host CPU
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can send commands to the serial adapter to read and write data from the memory
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system. The frontend server uses this functionality to load the test program
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into memory and to poll for completion of the program. More information on
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this can be found in :ref:`Customization/Boot-Process:Chipyard Boot Process`.
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Block Device Controller
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-----------------------
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The block device controller provides a generic interface for secondary storage.
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This device is primarily used in FireSim to interface with a block device
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software simulation model. The default Linux configuration in `firesim-software <https://github.com/firesim/firesim-software>`_
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To add a block device to your design, add the ``WithBlockDevice`` config fragment to your configuration.
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TileLink SERDES
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---------------
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The TileLink SERDES in the Test Chip IP library allow TileLink memory requests
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to be serialized so that they can be carried off chip through a serial link.
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The five TileLink channels are multiplexed over two SERDES channels, one in
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each direction.
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There are three different variants provided by the library, ``TLSerdes``
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exposes a manager interface to the chip, tunnels A, C, and E channels on
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its outbound link, and tunnels B and D channels on its inbound link. ``TLDesser``
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exposes a client interface to the chip, tunnels A, C, and E on its inbound link,
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and tunnels B and D on its outbound link. Finally, ``TLSerdesser`` exposes
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both client and manager interface to the chip and can tunnel all channels in
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both directions.
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For an example of how to use the SERDES classes, take a look at the
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``SerdesTest`` unit test in `the Test Chip IP unit test suite
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<https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/Unittests.scala>`_.
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TileLink Switcher
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-----------------
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The TileLink switcher is used when the chip has multiple possible memory
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interfaces and you would like to select which channels to map your memory
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requests to at boot time. It exposes a client node, multiple manager nodes,
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and a select signal. Depending on the setting of the select signal, requests
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from the client node will be directed to one of the manager nodes.
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The select signal must be set before any TileLink messages are sent and be
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kept stable throughout the remainder of operation. It is not safe to change
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the select signal once TileLink messages have begun sending.
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For an example of how to use the switcher, take a look at the ``SwitcherTest``
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unit test in the `Test Chip IP unit tests <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/Unittests.scala>`_.
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TileLink Ring Network
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---------------------
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TestChipIP provides a TLRingNetwork generator that has a similar interface
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to the TLXbar provided by RocketChip, but uses ring networks internally rather
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than crossbars. This can be useful for chips with very wide TileLink networks
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(many cores and L2 banks) that can sacrifice cross-section bandwidth to relieve
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wire routing congestion. Documentation on how to use the ring network can be
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found in :ref:`Customization/Memory-Hierarchy:The System Bus`. The implementation itself can be found
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`here <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/Ring.scala>`_,
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and may serve as an example of how to implement your own TileLink network with
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a different topology.
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UART Adapter
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------------
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The UART Adapter is a device that lives in the TestHarness and connects to the
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UART port of the DUT to simulate communication over UART (ex. printing out to UART
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during Linux boot). In addition to working with ``stdin/stdout`` of the host, it is able to
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output a UART log to a particular file using ``+uartlog=<NAME_OF_FILE>`` during simulation.
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By default, this UART Adapter is added to all systems within Chipyard by adding the
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``WithUART`` and ``WithUARTAdapter`` configs.
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SPI Flash Model
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---------------
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The SPI flash model is a device that models a simple SPI flash device. It currently
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only supports single read, quad read, single write, and quad write instructions. The
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memory is backed by a file which is provided using ``+spiflash#=<NAME_OF_FILE>``,
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where ``#`` is the SPI flash ID (usually ``0``).
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