ac5235e5ed
* Refactor how Configs parameterize the Top and TestHarnesses * Bump sha3, testchipip, icenet, firesim
28 lines
1.4 KiB
ReStructuredText
28 lines
1.4 KiB
ReStructuredText
.. _rocc-vs-mmio:
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RoCC vs MMIO
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------------
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Accelerators or custom IO devices can be added to your SoC in several ways:
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* MMIO Peripheral (a.k.a TileLink-Attached Accelerator)
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* Tightly-Coupled RoCC Accelerator
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These approaches differ in the method of the communication between the processor and the custom block.
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With the TileLink-Attached approach, the processor communicates with MMIO peripherals through memory-mapped registers.
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In contrast, the processor communicates with a RoCC accelerators through a custom protocol and custom non-standard ISA instructions reserved in the RISC-V ISA encoding space.
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Each core can have up to four accelerators that are controlled by custom instructions and share resources with the CPU.
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RoCC coprocessor instructions have the following form.
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.. code-block:: none
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customX rd, rs1, rs2, funct
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The X will be a number 0-3, and determines the opcode of the instruction, which controls which accelerator an instruction will be routed to.
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The ``rd``, ``rs1``, and ``rs2`` fields are the register numbers of the destination register and two source registers.
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The ``funct`` field is a 7-bit integer that the accelerator can use to distinguish different instructions from each other.
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Note that communication through a RoCC interface requires a custom software toolchain, whereas MMIO peripherals can use that standard toolchain with appropriate driver support.
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