233 lines
10 KiB
Makefile
233 lines
10 KiB
Makefile
#########################################################################################
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# makefile variables shared across multiple makefiles
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# - to use the help text, your Makefile should have a 'help' target that just
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# prints all the HELP_LINES
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#########################################################################################
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HELP_COMPILATION_VARIABLES =
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HELP_PROJECT_VARIABLES = \
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" SUB_PROJECT = use the specific subproject default variables [$(SUB_PROJECT)]" \
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" SBT_PROJECT = the SBT project that you should find the classes/packages in [$(SBT_PROJECT)]" \
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" MODEL = the top level module of the project in Chisel (normally the harness) [$(MODEL)]" \
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" VLOG_MODEL = the top level module of the project in Firrtl/Verilog (normally the harness) [$(VLOG_MODEL)]" \
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" MODEL_PACKAGE = the scala package to find the MODEL in [$(MODEL_PACKAGE)]" \
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" CONFIG = the configuration class to give the parameters for the project [$(CONFIG)]" \
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" CONFIG_PACKAGE = the scala package to find the CONFIG class [$(CONFIG_PACKAGE)]" \
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" GENERATOR_PACKAGE = the scala package to find the Generator class in [$(GENERATOR_PACKAGE)]" \
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" TB = testbench wrapper over the TestHarness needed to simulate in a verilog simulator [$(TB)]" \
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" TOP = top level module of the project (normally the module instantiated by the harness) [$(TOP)]"
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HELP_SIMULATION_VARIABLES = \
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" BINARY = riscv elf binary that the simulator will run when using the run-binary* targets" \
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" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]"
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# include default simulation rules
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HELP_COMMANDS = \
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" help = display this help" \
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" default = compiles non-debug simulator [./$(shell basename $(sim))]" \
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" debug = compiles debug simulator [./$(shell basename $(sim_debug))]" \
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" clean = remove all debug/non-debug simulators and intermediate files" \
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" clean-sim = removes non-debug simulator and simulator-generated files" \
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" clean-sim-debug = removes debug simulator and simulator-generated files"
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HELP_LINES = "" \
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" design specifier variables:" \
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" ---------------------------" \
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$(HELP_PROJECT_VARIABLES) \
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"" \
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" compilation variables:" \
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" ----------------------" \
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$(HELP_COMPILATION_VARIABLES) \
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"" \
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" simulation variables:" \
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" ---------------------" \
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$(HELP_SIMULATION_VARIABLES) \
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"" \
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" some useful general commands:" \
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" -----------------------------" \
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$(HELP_COMMANDS) \
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""
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#########################################################################################
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# subproject overrides
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# description:
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# - make it so that you only change 1 param to change most or all of them!
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# - mainly intended for quick developer setup for common flags
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#########################################################################################
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SUB_PROJECT ?= chipyard
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ifeq ($(SUB_PROJECT),chipyard)
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SBT_PROJECT ?= chipyard
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MODEL ?= TestHarness
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VLOG_MODEL ?= TestHarness
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MODEL_PACKAGE ?= $(SBT_PROJECT)
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CONFIG ?= RocketConfig
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CONFIG_PACKAGE ?= $(SBT_PROJECT)
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GENERATOR_PACKAGE ?= $(SBT_PROJECT)
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TB ?= TestDriver
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TOP ?= ChipTop
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endif
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# for Hwacha developers
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ifeq ($(SUB_PROJECT),hwacha)
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SBT_PROJECT ?= chipyard
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MODEL ?= TestHarness
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VLOG_MODEL ?= TestHarness
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MODEL_PACKAGE ?= freechips.rocketchip.system
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CONFIG ?= HwachaConfig
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CONFIG_PACKAGE ?= hwacha
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GENERATOR_PACKAGE ?= chipyard
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TB ?= TestDriver
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TOP ?= ExampleRocketSystem
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endif
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# For TestChipIP developers
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ifeq ($(SUB_PROJECT),testchipip)
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SBT_PROJECT ?= chipyard
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MODEL ?= TestHarness
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VLOG_MODEL ?= TestHarness
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MODEL_PACKAGE ?= chipyard.unittest
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CONFIG ?= TestChipUnitTestConfig
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CONFIG_PACKAGE ?= testchipip
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GENERATOR_PACKAGE ?= chipyard
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TB ?= TestDriver
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TOP ?= UnitTestSuite
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endif
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# For IceNet developers
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ifeq ($(SUB_PROJECT),icenet)
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SBT_PROJECT ?= chipyard
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MODEL ?= TestHarness
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VLOG_MODEL ?= TestHarness
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MODEL_PACKAGE ?= chipyard.unittest
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CONFIG ?= IceNetUnitTestConfig
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CONFIG_PACKAGE ?= icenet
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GENERATOR_PACKAGE ?= chipyard
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TB ?= TestDriver
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TOP ?= UnitTestSuite
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endif
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#########################################################################################
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# path to rocket-chip and testchipip
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#########################################################################################
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ROCKETCHIP_DIR = $(base_dir)/generators/rocket-chip
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ROCKETCHIP_RSRCS_DIR = $(ROCKETCHIP_DIR)/src/main/resources
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TESTCHIP_DIR = $(base_dir)/generators/testchipip
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TESTCHIP_RSRCS_DIR = $(TESTCHIP_DIR)/src/main/resources
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CHIPYARD_FIRRTL_DIR = $(base_dir)/tools/firrtl
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CHIPYARD_RSRCS_DIR = $(base_dir)/generators/chipyard/src/main/resources
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#########################################################################################
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# names of various files needed to compile and run things
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#########################################################################################
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long_name = $(MODEL_PACKAGE).$(MODEL).$(CONFIG)
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ifeq ($(GENERATOR_PACKAGE),hwacha)
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long_name=$(MODEL_PACKAGE).$(CONFIG)
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endif
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FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
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ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
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TOP_FILE ?= $(build_dir)/$(long_name).top.v
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TOP_FIR ?= $(build_dir)/$(long_name).top.fir
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TOP_ANNO ?= $(build_dir)/$(long_name).top.anno.json
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TOP_SMEMS_FILE ?= $(build_dir)/$(long_name).top.mems.v
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TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
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TOP_SMEMS_FIR ?= $(build_dir)/$(long_name).top.mems.fir
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HARNESS_FILE ?= $(build_dir)/$(long_name).harness.v
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HARNESS_FIR ?= $(build_dir)/$(long_name).harness.fir
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HARNESS_ANNO ?= $(build_dir)/$(long_name).harness.anno.json
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HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
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HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
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HARNESS_SMEMS_FIR ?= $(build_dir)/$(long_name).harness.mems.fir
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BOOTROM_FILES ?= bootrom.rv64.img bootrom.rv32.img
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BOOTROM_TARGETS ?= $(addprefix $(build_dir)/, $(BOOTROM_FILES))
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# files that contain lists of files needed for VCS or Verilator simulation
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SIM_FILE_REQS =
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sim_files ?= $(build_dir)/sim_files.f
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sim_top_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.top.f
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sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
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# single file that contains all files needed for VCS or Verilator simulation (unique and without .h's)
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sim_common_files ?= $(build_dir)/sim_files.common.f
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#########################################################################################
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# java arguments used in sbt
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#########################################################################################
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JAVA_HEAP_SIZE ?= 8G
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JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir=$(base_dir)/.java_tmp
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#########################################################################################
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# default sbt launch command
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#########################################################################################
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# by default build chisel3/firrtl and other subprojects from source
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SBT_OPTS_FILE := $(base_dir)/.sbtopts
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ifneq (,$(wildcard $(SBT_OPTS_FILE)))
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override SBT_OPTS += $(subst $$PWD,$(base_dir),$(shell cat $(SBT_OPTS_FILE)))
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endif
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SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES)
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SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
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ifdef ENABLE_SBT_THIN_CLIENT
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override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
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# enabling speeds up sbt loading
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# use with sbt script or sbtn to bypass error code issues
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SBT_CLIENT_FLAG = --client
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endif
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SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG)
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SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT))
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define run_scala_main
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cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
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endef
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FIRRTL_LOGLEVEL ?= error
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#########################################################################################
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# output directory for tests
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#########################################################################################
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output_dir=$(sim_dir)/output/$(long_name)
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#########################################################################################
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# helper variables to run binaries
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#########################################################################################
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PERMISSIVE_ON=+permissive
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PERMISSIVE_OFF=+permissive-off
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BINARY ?=
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LOADMEM ?=
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LOADMEM_ADDR ?= 81000000
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override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
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ifneq ($(LOADMEM),)
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override SIM_FLAGS += +loadmem=$(LOADMEM) +loadmem_addr=$(LOADMEM_ADDR)
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endif
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VERBOSE_FLAGS ?= +verbose
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sim_out_name = $(output_dir)/$(subst $() $(),_,$(notdir $(basename $(BINARY))))
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binary_hex= $(sim_out_name).loadmem_hex
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#########################################################################################
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# build output directory for compilation
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#########################################################################################
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gen_dir=$(sim_dir)/generated-src
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build_dir=$(gen_dir)/$(long_name)
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#########################################################################################
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# vsrcs needed to run projects
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#########################################################################################
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rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
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#########################################################################################
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# sources needed to run simulators
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#########################################################################################
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sim_vsrcs = \
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$(TOP_FILE) \
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$(HARNESS_FILE) \
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$(TOP_SMEMS_FILE) \
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$(HARNESS_SMEMS_FILE)
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#########################################################################################
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# assembly/benchmark variables
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#########################################################################################
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timeout_cycles = 10000000
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bmark_timeout_cycles = 100000000
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