38 lines
1.4 KiB
Scala
38 lines
1.4 KiB
Scala
// See LICENSE for license details.
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package chipyard.fpga.nexysvideo
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import chisel3._
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import freechips.rocketchip.subsystem.{PeripheryBusKey}
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import freechips.rocketchip.tilelink.{TLBundle}
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import freechips.rocketchip.util.{HeterogeneousBag}
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import freechips.rocketchip.diplomacy.{LazyRawModuleImp}
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import sifive.blocks.devices.uart.{UARTParams}
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import chipyard._
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import chipyard.harness._
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import chipyard.iobinders._
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class WithNexysVideoUARTTSI(uartBaudRate: BigInt = 115200) extends HarnessBinder({
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case (th: HasHarnessInstantiators, port: UARTTSIPort, chipId: Int) => {
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val nexysvideoth = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
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nexysvideoth.io_uart_bb.bundle <> port.io.uart
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nexysvideoth.other_leds(1) := port.io.dropped
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nexysvideoth.other_leds(2) := port.io.tsi2tl_state(0)
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nexysvideoth.other_leds(3) := port.io.tsi2tl_state(1)
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nexysvideoth.other_leds(4) := port.io.tsi2tl_state(2)
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nexysvideoth.other_leds(5) := port.io.tsi2tl_state(3)
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}
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})
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class WithNexysVideoDDRTL extends HarnessBinder({
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case (th: HasHarnessInstantiators, port: TLMemPort, chipId: Int) => {
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val nexysTh = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[NexysVideoHarness]
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val bundles = nexysTh.ddrClient.get.out.map(_._1)
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val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
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bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
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ddrClientBundle <> port.io
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}
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})
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