Files

Abraham Gonzalez 85b555dbce NVDLA Integration + Cleanup Ariane Preprocessing (#505 )

* [nvdla] initial nvdla integration

* [nvdla] add firesim configs

* [nvdla] re-add accidentally deleted line

* [nvdla] works on master with small

* [nvdla] use master branch of nvdla

* [nvdla] remove extra sources

* [nvdla] bump

* [nvdla + ariane] bump and use insert-includes for pre-processing

* [nvdla] add ci | remove target configs in FireChip | update naming

* [nvdla] bump nvdla | fix ci run-tests error

* [nvdla] re-enable PCWM-L error | fix/update makefile(s)

* [nvdla] bump nvdla fragments in FireChip

* [misc] bump tutorial patches

* [chipyard] remove extra import

* [nvdla] bump nvdla for pbus [ci skip]

* [nvdla] update firemarshal and add nvdla workload

* [nvdla] bump nvdla-workload

* [nvdla] bump hw

* [docs] add basic documentation

* [docs] adjustments to documentation

* [misc] update docs | bump firesim with recipe

* [misc] disable error on warnings in verilator | bump number width to match RC

* [docs] fix doc build error

* [verilator] move no fail on warning to be global

* [ci skip] [nvdla] bump submodule urls

* [misc] move firesim specific configs into nvdla dir [ci skip]

* [nvdla] fix run-tests in ci

* update RC configs | bump marshal | bump nvdla-workload

* [nvdla] bump nvdla-workload [ci skip]

* add topology mixin to nvdla configs

* update tutorial patches

2020-05-16 12:22:30 -07:00

4.2 KiB

Raw Blame History

Chipyard Framework

Using Chipyard

To get started using Chipyard, see the documentation on the Chipyard documentation site: https://chipyard.readthedocs.io/

What is Chipyard

Chipyard is an open source framework for agile development of Chisel-based systems-on-chip. It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other Berkeley projects to produce a RISC-V SoC with everything from MMIO-mapped peripherals to custom accelerators. Chipyard contains processor cores (Rocket, BOOM, Ariane), accelerators (Hwacha, Gemmini, NVDLA), memory systems, and additional peripherals and tooling to help create a full featured SoC. Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation (FireSim), automated VLSI flows (Hammer), and software workload generation for bare-metal and Linux-based systems (FireMarshal). Chipyard is actively developed in the Berkeley Architecture Research Group in the Electrical Engineering and Computer Sciences Department at the University of California, Berkeley.

Resources

Chipyard Documentation: https://chipyard.readthedocs.io/
Chipyard Basics slides: https://fires.im/micro19-slides-pdf/02_chipyard_basics.pdf
Chipyard Tutorial Exercise slides: https://fires.im/micro19-slides-pdf/03_building_custom_socs.pdf

Need help?

Join the Chipyard Mailing List: https://groups.google.com/forum/#!forum/chipyard
If you find a bug, post an issue on this repo

Contributing

See CONTRIBUTING.md

These publications cover many of the internal components used in Chipyard. However, for the most up-to-date details, users should refer to the Chipyard docs.

Generators
- Rocket Chip: K. Asanovic, et al., UCB EECS TR. PDF.
- BOOM: C. Celio, et al., Hot Chips 30. PDF.
- Hwacha: Y. Lee, et al., ESSCIRC'14. PDF.
- Gemmini: H. Genc, et al., arXiv. PDF.
Sims
- FireSim: S. Karandikar, et al., ISCA'18. PDF.
  - FireSim Micro Top Picks: S. Karandikar, et al., IEEE Micro, Top Picks 2018. PDF.
  - FASED: D. Biancolin, et al., FPGA'19. PDF.
  - Golden Gate: A. Magyar, et al., ICCAD'19. PDF.
  - FirePerf: S. Karandikar, et al., ASPLOS'20. PDF.
Tools
- Chisel: J. Bachrach, et al., DAC'12. PDF.
- FIRRTL: A. Izraelevitz, et al., ICCAD'17. PDF.
- Chisel DSP: A. Wang, et al., DAC'18. PDF.
VLSI
- Hammer: E. Wang, et al., ISQED'20. PDF.

4.2 KiB Raw Blame History