63 lines
2.2 KiB
Scala
63 lines
2.2 KiB
Scala
package example
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import chisel3._
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import chisel3.internal.sourceinfo.{SourceInfo}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import boom.system.{BoomTilesKey}
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/**
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* Example top with periphery devices and ports, and a BOOM subsystem
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*/
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class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem
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with HasAsyncExtInterrupts
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with boom.system.CanHaveMisalignedMasterAXI4MemPort
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with CanHaveMasterAXI4MMIOPort
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with CanHaveSlaveAXI4Port
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with HasPeripheryBootROM
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{
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override lazy val module = new ExampleBoomAndRocketSystemModule(this)
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// The sbus masters the cbus; here we convert TL-UH -> TL-UL
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sbus.crossToBus(cbus, NoCrossing)
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// The cbus masters the pbus; which might be clocked slower
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cbus.crossToBus(pbus, SynchronousCrossing())
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// The fbus masters the sbus; both are TL-UH or TL-C
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FlipRendering { implicit p =>
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sbus.crossFromBus(fbus, SynchronousCrossing())
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}
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// The sbus masters the mbus; here we convert TL-C -> TL-UH
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private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
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private val (in, out, halt) = coherenceManager(this)
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if (nBanks != 0) {
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sbus.coupleTo("coherence_manager") { in :*= _ }
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mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
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}
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}
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/**
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* Example top module with periphery devices and ports, and a BOOM subsystem
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*/
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class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer)
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with HasRTCModuleImp
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with HasExtInterruptsModuleImp
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with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp
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with CanHaveMasterAXI4MMIOPortModuleImp
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with CanHaveSlaveAXI4PortModuleImp
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with HasPeripheryBootROMModuleImp
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with DontTouch
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