63 lines
2.4 KiB
Scala
63 lines
2.4 KiB
Scala
// See LICENSE for license details.
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package chipyard.fpga.arty100t
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.uart._
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import sifive.fpgashells.shell.{DesignKey}
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import testchipip.{SerialTLKey}
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import chipyard.{BuildSystem}
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// don't use FPGAShell's DesignKey
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class WithNoDesignKey extends Config((site, here, up) => {
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case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
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})
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// By default, this uses the on-board USB-UART for the TSI-over-UART link
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// The PMODUART HarnessBinder maps the actual UART device to JD pin
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class WithArty100TTweaks(freqMHz: Double = 50) extends Config(
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new WithArty100TPMODUART ++
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new WithArty100TUARTTSI ++
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new WithArty100TDDRTL ++
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new WithArty100TJTAG ++
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new WithNoDesignKey ++
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new testchipip.WithUARTTSIClient ++
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new chipyard.harness.WithSerialTLTiedOff ++
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new chipyard.harness.WithHarnessBinderClockFreqMHz(freqMHz) ++
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new chipyard.config.WithMemoryBusFrequency(freqMHz) ++
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new chipyard.config.WithFrontBusFrequency(freqMHz) ++
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new chipyard.config.WithSystemBusFrequency(freqMHz) ++
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new chipyard.config.WithPeripheryBusFrequency(freqMHz) ++
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new chipyard.config.WithControlBusFrequency(freqMHz) ++
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new chipyard.config.WithOffchipBusFrequency(freqMHz) ++
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new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
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new chipyard.clocking.WithPassthroughClockGenerator ++
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new chipyard.config.WithTLBackingMemory ++ // FPGA-shells converts the AXI to TL for us
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new freechips.rocketchip.subsystem.WithExtMemSize(BigInt(256) << 20) ++ // 256mb on ARTY
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new freechips.rocketchip.subsystem.WithoutTLMonitors)
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class RocketArty100TConfig extends Config(
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new WithArty100TTweaks ++
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new chipyard.config.WithBroadcastManager ++ // no l2
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new chipyard.RocketConfig)
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class NoCoresArty100TConfig extends Config(
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new WithArty100TTweaks ++
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new chipyard.config.WithBroadcastManager ++ // no l2
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new chipyard.NoCoresConfig)
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// This will fail to close timing above 50 MHz
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class BringupArty100TConfig extends Config(
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new WithArty100TSerialTLToGPIO ++
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new WithArty100TTweaks(freqMHz = 50) ++
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new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(50)) ++
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new chipyard.ChipBringupHostConfig)
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