abejgonzalez 929110f562 add large boom hwacha config

2019-10-18 16:18:16 -07:00

..

boom @ 2a0ea2e7ac

[firechip] remove fireboom DUT, remove ExcludeInvalidBoomAssertions mixin

2019-10-08 01:03:47 +00:00

example/src/main

add large boom hwacha config

2019-10-18 16:18:16 -07:00

firechip/src

Add FireChip target with Verilog blackbox (#297)

2019-10-16 14:31:58 -07:00

hwacha @ ff4605f5d1

Bump hwacha

2019-05-17 18:38:11 -07:00

icenet @ baa40ed85d

make BlockDevice, SerialAdapter, and IceNIC connect to fbus/pbus instead of sbus

2019-08-22 10:42:37 -07:00

rocket-chip @ 50de8a34c1

bump rc/firrtl | bump to temp boom/testchipip

2019-06-28 11:07:41 -07:00

sha3 @ 60ddfe7c5b

update build.sbt for sha3 to build midastargetutils | have midas printf parameterized in sha3

2019-10-10 00:46:04 +00:00

sifive-blocks @ 24dd537894

add sifive blocks | add rebar configs for boom

2019-04-19 21:06:32 -07:00

sifive-cache @ 13d0c2f178

add InclusiveCache

2019-07-02 16:58:08 -07:00

testchipip @ aa13f6ccc1

make BlockDevice, SerialAdapter, and IceNIC connect to fbus/pbus instead of sbus

2019-08-22 10:42:37 -07:00

tracegen/src/main/scala

add tracegen project

2019-08-30 11:38:07 -07:00

utilities/src/main

[system] Comment on hart-ordering restriction

2019-10-07 17:27:47 -07:00