151 lines
7.6 KiB
ReStructuredText
151 lines
7.6 KiB
ReStructuredText
.. _chipyard-components:
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Chipyard Components
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===============================
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Generators
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-------------------------------------------
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The Chipyard Framework currently consists of the following RTL generators:
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Processor Cores
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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**Rocket Core**
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An in-order RISC-V core.
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See :ref:`Generators/Rocket:Rocket Core` for more information.
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**BOOM (Berkeley Out-of-Order Machine)**
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An out-of-order RISC-V core.
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See :ref:`Generators/BOOM:Berkeley Out-of-Order Machine (BOOM)` for more information.
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**CVA6 Core**
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An in-order RISC-V core written in System Verilog. Previously called Ariane.
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See :ref:`Generators/CVA6:CVA6 Core` for more information.
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**Ibex Core**
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An in-order 32 bit RISC-V core written in System Verilog.
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See :ref:`Generators/Ibex:Ibex Core` for more information.
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Accelerators
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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**Hwacha**
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A decoupled vector architecture co-processor.
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Hwacha currently implements a non-standard RISC-V extension, using a vector architecture programming model.
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Hwacha integrates with a Rocket or BOOM core using the RoCC (Rocket Custom Co-processor) interface.
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See :ref:`Generators/Hwacha:Hwacha` for more information.
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**Gemmini**
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A matrix-multiply accelerator targeting neural-networks
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**SHA3**
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A fixed-function accelerator for the SHA3 hash function. This simple accelerator is used as a demonstration for some of the
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Chipyard integration flows using the RoCC interface.
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System Components:
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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**constellation**
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A generator for network-on-chip (NoC) interconnects.
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**icenet**
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A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.
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**rocket-chip-blocks**
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System components originally implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
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Now maintained by Chips Alliance. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
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**AWL (Analog Widget Library)**
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Digital components required for integration with high speed serial links.
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**testchipip**
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A collection of utilities used for testing chips and interfacing them with larger test environments.
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Tools
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-------------------------------------------
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**Chisel**
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A hardware description library embedded in Scala.
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Chisel is used to write RTL generators using meta-programming, by embedding hardware generation primitives in the Scala programming language.
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The Chisel compiler elaborates the generator into a FIRRTL output.
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See :ref:`Tools/Chisel:Chisel` for more information.
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**FIRRTL**
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An intermediate representation library for RTL description of digital designs.
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FIRRTL is used as a formalized digital circuit representation between Chisel and Verilog.
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FIRRTL enables digital circuits manipulation between Chisel elaboration and Verilog generation.
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See :ref:`Tools/FIRRTL:FIRRTL` for more information.
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**Tapeout-Tools (Formerly Barstools)**
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A collection of common FIRRTL transformations used to manipulate a digital circuit without changing the generator source RTL.
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See :ref:`Tools/Tapeout-Tools:Tapeout-Tools` for more information.
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**Dsptools**
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A Chisel library for writing custom signal processing hardware, as well as integrating custom signal processing hardware into an SoC (especially a Rocket-based SoC).
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Toolchains
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-------------------------------------------
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**riscv-tools**
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A collection of software toolchains used to develop and execute software on the RISC-V ISA.
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The include compiler and assembler toolchains, functional ISA simulator (spike), the Berkeley Boot Loader (BBL) and proxy kernel.
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The riscv-tools repository was previously required to run any RISC-V software, however, many of the riscv-tools components have since been upstreamed to their respective open-source projects (Linux, GNU, etc.).
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Nevertheless, for consistent versioning, as well as software design flexibility for custom hardware, we include the riscv-tools repository and installation in the Chipyard framework.
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**esp-tools**
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A fork of riscv-tools, designed to work with the Hwacha non-standard RISC-V extension.
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This fork can also be used as an example demonstrating how to add additional RoCC accelerators to the ISA-level simulation (Spike) and the higher-level software toolchain (GNU binutils, riscv-opcodes, etc.)
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Software
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-------------------------------------------
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**FireMarshal**
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FireMarshal is the default workload generation tool that Chipyard uses to create software to run on its platforms.
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See :ref:`fire-marshal` for more information.
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**Baremetal-IDE**
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Baremetal-IDE is an all-in-one tool for baremetal-level C/C++ program development. See `Tutorial <https://ucb-bar.gitbook.io/chipyard/baremetal-ide/getting-started-with-baremetal-ide/>`_ for more information.
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Sims
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-------------------------------------------
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**Verilator**
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Verilator is an open source Verilog simulator.
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The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
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See :ref:`Simulation/Software-RTL-Simulation:Verilator (Open-Source)` for more information.
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**VCS**
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VCS is a proprietary Verilog simulator.
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Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
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See :ref:`Simulation/Software-RTL-Simulation:Synopsys VCS (License Required)` for more information.
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**FireSim**
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FireSim is an open-source FPGA-accelerated simulation platform, using Amazon Web Services (AWS) EC2 F1 instances on the public cloud.
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FireSim automatically transforms and instruments open-hardware designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre-silicon verification and performance validation.
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To model I/O, FireSim includes synthesizeable and timing-accurate models for standard interfaces like DRAM, Ethernet, UART, and others.
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The use of the elastic public cloud enable FireSim to scale simulations up to thousands of nodes.
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In order to use FireSim, the repository must be cloned and executed on AWS instances.
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See :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim` for more information.
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Prototyping
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-------------------------------------------
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**FPGA Prototyping**
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FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``.
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Some examples of FPGAs supported are the Xilinx Arty 35T and VCU118 boards.
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For a fast and deterministic simulation with plenty of debugging tools, please consider using the :ref:`Simulation/FPGA-Accelerated-Simulation:FireSim` platform.
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See :ref:`Prototyping/index:Prototyping Flow` for more information on FPGA prototypes.
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VLSI
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-------------------------------------------
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**Hammer**
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Hammer is a VLSI flow designed to provide a layer of abstraction between general physical design concepts to vendor-specific EDA tool commands.
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The HAMMER flow provide automated scripts which generate relevant tool commands based on a higher level description of physical design constraints.
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The Hammer flow also allows for re-use of process technology knowledge by enabling the construction of process-technology-specific plug-ins, which describe particular constraints relating to that process technology (obsolete standard cells, metal layer routing constraints, etc.).
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The Hammer flow requires access to proprietary EDA tools and process technology libraries.
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See :ref:`VLSI/Hammer:Core HAMMER` for more information.
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