30 lines
1.4 KiB
Scala
30 lines
1.4 KiB
Scala
package chipyard.config
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import org.chipsalliance.cde.config.{Config}
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.diplomacy.{DTSTimebase}
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import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
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// Replaces the L2 with a broadcast manager for maintaining coherence
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class WithBroadcastManager extends Config((site, here, up) => {
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case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
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})
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class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => {
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case BroadcastKey => params
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})
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class WithSystemBusWidth(bitWidth: Int) extends Config((site, here, up) => {
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case SystemBusKey => up(SystemBusKey, site).copy(beatBytes=bitWidth/8)
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})
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// Adds buffers on the interior of the inclusive LLC, to improve PD
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class WithInclusiveCacheInteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
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case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerInterior=buffer, bufOuterInterior=buffer)
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})
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// Adds buffers on the exterior of the inclusive LLC, to improve PD
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class WithInclusiveCacheExteriorBuffer(buffer: InclusiveCachePortParameters = InclusiveCachePortParameters.full) extends Config((site, here, up) => {
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case InclusiveCacheKey => up(InclusiveCacheKey).copy(bufInnerExterior=buffer, bufOuterExterior=buffer)
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})
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