29 lines
2.4 KiB
ReStructuredText
29 lines
2.4 KiB
ReStructuredText
Running a Design on Arty
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========================
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Basic Design
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------------
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The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins.
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The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide <https://static.dev.sifive.com/SiFive-E310-arty-gettingstarted-v1.0.6.pdf>`__.
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The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb.
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To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``.
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Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config.
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.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala
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:language: scala
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:start-after: DOC include start: AbstractArty and Rocket
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:end-before: DOC include end: AbstractArty and Rocket
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Future peripherals to be supported include the Arty's SPI Flash EEPROM.
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Brief Implementation Description and Guidance for Adding/Changing Xilinx Collateral
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-----------------------------------------------------------------------------------
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The basis for the Arty design is the creation of a special test harness that connects the external FPGA IO (which exist as Xilinx IP blackboxes) to the Chipyard design.
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This is done with the ``ArtyTestHarness`` in the basic default Arty target.
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However, unlike the more complicated ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects ``ChipTop`` IO to the ports of the external FPGA IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``.
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Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``.
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If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``.
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The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the ``ChipTop`` using ``HarnessBinders`` and ``IOBinders``.
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