34 lines
1.4 KiB
ReStructuredText
34 lines
1.4 KiB
ReStructuredText
Open Source Simulators
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Verilator
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-----------------------
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Verilator is an open-source LGPL-Licensed simulator maintained by `Veripool <https://www.veripool.org/>`__
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The ReBAR framework can download, build, and execute simulations using Verilator.
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To run a simulation using verilator, perform the following steps:
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To compile the example design, run make in the ``sims/verisim`` directory.
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This will elaborate the DefaultExampleConfig in the example project.
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An executable called simulator-example-DefaultExampleConfig will be produced.
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This executable is a simulator that has been compiled based on the design that was built.
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You can then use this executable to run any compatible RV64 code. For instance,
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to run one of the riscv-tools assembly tests.
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::
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./simulator-example-DefaultExampleConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
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If you later create your own project, you can use environment variables to
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build an alternate configuration.
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::
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make PROJECT=yourproject CONFIG=YourConfig
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./simulator-yourproject-YourConfig ...
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If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``. This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer. An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>__
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