Abraham Gonzalez b554b3acde Merge pull request #572 from ucb-bar/make-chiptop-synthesizable ...

Move all non-synthesizable constructs into the test harness

2020-05-27 10:39:02 -07:00

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ariane @ d914fc8f03

NVDLA Integration + Cleanup Ariane Preprocessing (#505)

2020-05-16 12:22:30 -07:00

boom @ f0caca8d6b

[traceio] wdata: use option instead of 1.B wire

2020-05-16 14:47:15 -07:00

chipyard/src/main

Merge pull request #572 from ucb-bar/make-chiptop-synthesizable

2020-05-27 10:39:02 -07:00

firechip/src

Remove commented code in ScalaTests

2020-05-19 00:50:14 +00:00

gemmini @ d6f36d37d1

bump gemmini to v0.2 (#469)

2020-03-13 18:34:36 -07:00

hwacha @ 2706502daf

Rocket Chip Stage/Phase Bump (#503)

2020-04-18 17:54:27 +00:00

icenet @ 705ca50690

get icenet and testchipip unit tests working

2020-04-28 10:32:28 -07:00

nvdla @ b2b78c9f89

NVDLA Integration + Cleanup Ariane Preprocessing (#505)

2020-05-16 12:22:30 -07:00

rocket-chip @ 1872f5d501

bump rocket chisel (3.3) and firrtl (1.3)

2020-05-05 11:02:28 -07:00

sha3 @ cec8db9d6b

Add tutorial config and tutorial patches

2020-03-05 19:44:37 -08:00

sifive-blocks @ c1dee8234c

Bump sifive-blocks

2020-05-05 13:58:01 -07:00

sifive-cache @ 4ebefa3e30

sifive cache bump to RC firrtl 1.3

2020-05-12 23:34:01 -07:00

testchipip @ b02bd8eaca

bump testchipip

2020-05-18 12:21:17 -07:00

tracegen

BOOM Bump w. Fromajo (#523)

2020-05-16 00:21:24 -07:00

utilities/src/main

Upgrade verilator to support permissive args in the same way as vcs

2020-05-24 09:29:22 -07:00