Files
chipyard/fpga
Tingyuan LIANG d06abdb419 Swap two arguments to resolve bug
**Related issue**: N/A

**Type of change**: bug fix

**Impact**: other

**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](d4b3878e4f/xilinx/common/tcl/prologue.tcl)
Swaping the two arguments can resolve bug.
2021-08-12 23:22:41 +08:00
..
2020-11-12 16:24:10 -08:00
2021-04-03 12:55:27 -07:00
2021-08-12 23:22:41 +08:00