44 lines
1.4 KiB
Scala
44 lines
1.4 KiB
Scala
// See LICENSE for license details.
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package chipyard.fpga.arty
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.uart._
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import testchipip.serdes.{SerialTLKey}
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import chipyard.{BuildSystem}
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// DOC include start: AbstractArty and Rocket
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class WithArtyTweaks extends Config(
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new WithArtyDebugResetHarnessBinder ++
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new WithArtyJTAGResetHarnessBinder ++
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new WithArtyJTAGHarnessBinder ++
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new WithArtyUARTHarnessBinder ++
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new WithDebugResetPassthrough ++
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new chipyard.harness.WithHarnessBinderClockFreqMHz(32) ++
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new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
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new chipyard.config.WithDTSTimebase(32000) ++
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new chipyard.config.WithSystemBusFrequency(32) ++
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new chipyard.config.WithFrontBusFrequency(32) ++
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new chipyard.config.WithControlBusFrequency(32) ++
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new chipyard.config.WithPeripheryBusFrequency(32) ++
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new chipyard.config.WithControlBusFrequency(32) ++
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new testchipip.serdes.WithNoSerialTL ++
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new testchipip.soc.WithNoScratchpads
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)
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class TinyRocketArtyConfig extends Config(
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new WithArtyTweaks ++
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new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
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new chipyard.TinyRocketConfig
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)
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// DOC include end: AbstractArty and Rocket
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