91 lines
3.6 KiB
Scala
91 lines
3.6 KiB
Scala
package chipyard.fpga.vcu118
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import sys.process._
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import org.chipsalliance.cde.config.{Config, Parameters}
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import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
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import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
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import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
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import freechips.rocketchip.tile.{XLen}
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import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
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import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
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import sifive.fpgashells.shell.{DesignKey}
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import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD, VCU118DDRSize}
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import testchipip.serdes.{SerialTLKey}
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import chipyard._
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import chipyard.harness._
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class WithDefaultPeripherals extends Config((site, here, up) => {
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case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
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case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L)))
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case VCU118ShellPMOD => "SDIO"
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})
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class WithSystemModifications extends Config((site, here, up) => {
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case DTSTimebase => BigInt((1e6).toLong)
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case BootROMLocated(x) => up(BootROMLocated(x), site).map { p =>
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// invoke makefile for sdboot
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val freqMHz = (site(SystemBusKey).dtsFrequency.get / (1000 * 1000)).toLong
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val make = s"make -C fpga/src/main/resources/vcu118/sdboot PBUS_CLK=${freqMHz} bin"
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require (make.! == 0, "Failed to build bootrom")
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p.copy(hang = 0x10000, contentFileName = s"./fpga/src/main/resources/vcu118/sdboot/build/sdboot.bin")
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}
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case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) // set extmem to DDR size
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case SerialTLKey => Nil // remove serialized tl port
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})
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// DOC include start: AbstractVCU118 and Rocket
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class WithVCU118Tweaks extends Config(
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// clocking
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new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
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new chipyard.clocking.WithPassthroughClockGenerator ++
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new chipyard.config.WithMemoryBusFrequency(100) ++
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new chipyard.config.WithSystemBusFrequency(100) ++
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new chipyard.config.WithControlBusFrequency(100) ++
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new chipyard.config.WithPeripheryBusFrequency(100) ++
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new chipyard.config.WithControlBusFrequency(100) ++
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new WithFPGAFrequency(100) ++ // default 100MHz freq
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// harness binders
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new WithUART ++
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new WithSPISDCard ++
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new WithDDRMem ++
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// other configuration
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new WithDefaultPeripherals ++
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new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
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new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
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new chipyard.config.WithNoDebug ++ // remove debug module
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
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)
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class RocketVCU118Config extends Config(
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new WithVCU118Tweaks ++
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new chipyard.RocketConfig
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)
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// DOC include end: AbstractVCU118 and Rocket
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class BoomVCU118Config extends Config(
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new WithFPGAFrequency(50) ++
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new WithVCU118Tweaks ++
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new chipyard.MegaBoomConfig
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)
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class WithFPGAFrequency(fMHz: Double) extends Config(
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new chipyard.harness.WithHarnessBinderClockFreqMHz(fMHz) ++
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new chipyard.config.WithSystemBusFrequency(fMHz) ++
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new chipyard.config.WithPeripheryBusFrequency(fMHz) ++
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new chipyard.config.WithControlBusFrequency(fMHz) ++
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new chipyard.config.WithFrontBusFrequency(fMHz) ++
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new chipyard.config.WithMemoryBusFrequency(fMHz)
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)
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class WithFPGAFreq25MHz extends WithFPGAFrequency(25)
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class WithFPGAFreq50MHz extends WithFPGAFrequency(50)
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class WithFPGAFreq75MHz extends WithFPGAFrequency(75)
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class WithFPGAFreq100MHz extends WithFPGAFrequency(100)
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