72 lines
2.7 KiB
ReStructuredText
72 lines
2.7 KiB
ReStructuredText
Rocket Chip
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===========
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Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
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`SiFive <https://www.sifive.com>`__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
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`Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
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Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip
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uses Rocket core CPUs by default, it can also be configured to use the BOOM
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out-of-order core generator or some other custom CPU generator instead.
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A detailed diagram of a typical Rocket Chip system is shown below.
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.. image:: ../_static/images/rocketchip-diagram.png
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Tiles
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-----
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The diagram shows a dual-core ``Rocket`` system. Each ``Rocket`` core is
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grouped with a page-table walker, L1 instruction cache, and L1 data cache into
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a ``RocketTile``.
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The ``Rocket`` core can also be swapped for a ``BOOM`` core. Each tile can
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also be configured with a RoCC accelerator that connects to the core as a
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coprocessor.
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Memory System
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-------------
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The tiles connect to the ``SystemBus``, which connect it to the L2 cache banks.
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The L2 cache banks then connect to the ``MemoryBus``, which connects to the
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DRAM controller through a TileLink to AXI converter.
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To learn more about the memory hierarchy, see :ref:`Memory Hierarchy`.
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MMIO
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----
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For MMIO peripherals, the ``SystemBus`` connects to the ``ControlBus`` and ``PeripheryBus``.
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The ``ControlBus`` attaches standard peripherals like the BootROM, the
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Platform-Level Interrupt Controller (PLIC), the core-local interrupts (CLINT),
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and the Debug Unit.
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The BootROM contains the first stage bootloader, the first instructions to run
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when the system comes out of reset. It also contains the Device Tree, which is
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used by Linux to determine what other peripherals are attached.
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The PLIC aggregates and masks device interrupts and external interrupts.
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The core-local interrupts include software interrupts and timer interrupts for
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each CPU.
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The Debug Unit is used to control the chip externally. It can be used to load
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data and instructions to memory or pull data from memory. It can be controlled
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through a custom DMI or standard JTAG protocol.
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The ``PeripheryBus`` attaches additional peripherals like the NIC and Block Device.
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It can also optionally expose an external AXI4 port, which can be attached to
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vendor-supplied AXI4 IP.
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To learn more about adding MMIO peripherals, check out the :ref:`mmio-accelerators`
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section.
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DMA
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---
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You can also add DMA devices that read and write directly from the memory
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system. These are attached to the ``FrontendBus``. The ``FrontendBus`` can also
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connect vendor-supplied AXI4 DMA devices through an AXI4 to TileLink converter.
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To learn more about adding DMA devices, see the :ref:`dma-devices` section.
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