36 lines
1.6 KiB
ReStructuredText
36 lines
1.6 KiB
ReStructuredText
Open Source Software RTL Simulators
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Verilator
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-----------------------
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`Verilator <https://www.veripool.org/wiki/verilator>`__ is an open-source LGPL-Licensed simulator maintained by `Veripool <https://www.veripool.org/>`__.
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The REBAR framework can download, build, and execute simulations using Verilator.
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To run a simulation using Verilator, perform the following steps:
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To compile the example design, run ``make`` in the ``sims/verisim`` directory.
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This will elaborate the ``DefaultRocketConfig`` in the example project.
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An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
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This executable is a simulator that has been compiled based on the design that was built.
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You can then use this executable to run any compatible RV64 code.
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For instance, to run one of the riscv-tools assembly tests.
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.. code-block:: shell
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./simulator-example-DefaultRocketConfig $RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv64ui-p-simple
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If you later create your own project, you can use environment variables to build an alternate configuration.
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.. code-block:: shell
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make SUB_PROJECT=yourproject
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./simulator-<yourproject>-<yourconfig> ...
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If you would like to extract waveforms from the simulation, run the command ``make debug`` instead of just ``make``.
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This will generate a vcd file (vcd is a standard waveform representation file format) that can be loaded to any common waveform viewer.
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An open-source vcd-capable waveform viewer is `GTKWave <http://gtkwave.sourceforge.net/>`__.
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Please refer to :ref:`Running A Simulation` for a step by step tutorial on how to get a simulator up and running.
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