100 lines
3.6 KiB
Scala
100 lines
3.6 KiB
Scala
package chipyard.fpga.vcu118.bringup
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import chisel3._
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import freechips.rocketchip.diplomacy._
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import org.chipsalliance.cde.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.prci._
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import sifive.fpgashells.shell.xilinx._
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import sifive.fpgashells.ip.xilinx._
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import sifive.fpgashells.shell._
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import sifive.fpgashells.clocks._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.i2c._
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import sifive.blocks.devices.gpio._
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import testchipip.tsi.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO}
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import testchipip.util.{TLSinkSetter}
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import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
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import chipyard.{ChipTop}
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import chipyard.harness._
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class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118FPGATestHarness {
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/*** UART ***/
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require(dp(PeripheryUARTKey).size == 2)
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// 2nd UART goes to the FMC UART
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val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
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val io_fmc_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
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dp(UARTOverlayKey).last.place(UARTDesignInput(io_fmc_uart_bb))
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/*** I2C ***/
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val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
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val io_i2c_bb = BundleBridgeSource(() => (new I2CPort))
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dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb))
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/*** GPIO ***/
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val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
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val maxGPIOSupport = 32 // max gpio per gpio chip
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val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
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Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
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})
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val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
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(dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
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placer.place(GPIODesignInput(params, io_gpio_bb(i)))
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}
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/*** TSI Host Widget ***/
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require(dp(PeripheryTSIHostKey).size == 1)
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// use the 2nd system clock for the 2nd DDR
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val sysClk2Node = dp(ClockInputOverlayKey).last.place(ClockInputDesignInput()).overlayOutput.node
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val ddr2PLL = dp(PLLFactoryKey)()
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ddr2PLL := sysClk2Node
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val ddr2Clock = ClockSinkNode(freqMHz = dp(FPGAFrequencyKey))
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val ddr2Wrangler = LazyModule(new ResetWrangler)
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val ddr2Group = ClockGroup()
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ddr2Clock := ddr2Wrangler.node := ddr2Group := ddr2PLL
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val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput()))
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val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr
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val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth)))
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dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb))
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// connect 1 mem. channel to the FPGA DDR
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val tsiDdrClient = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
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name = "chip_ddr",
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sourceId = IdRange(0, 64)
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)))))
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(ddr2Node
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:= TLFragmenter(8,64,holdFirstDeny=true)
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:= TLCacheCork()
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:= TLAtomicAutomata(passthrough=false)
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:= TLSinkSetter(64)
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:= tsiDdrClient)
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// module implementation
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override lazy val module = new BringupVCU118FPGATestHarnessImp(this)
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}
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class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) {
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lazy val bringupOuter = _outer
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}
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