49 lines
1.9 KiB
ReStructuredText
49 lines
1.9 KiB
ReStructuredText
Debugging with DTM/JTAG
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===============================
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By default, Chipyard is not setup to use the Debug Test Module (DTM) to bringup the core.
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Instead, Chipyard uses TSI commands to bringup the core (which normally results in a faster simulation).
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However, if you want to use JTAG, you must do the following steps to setup a DTM enabled system.
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Creating a DTM/JTAG Config
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-------------------------------------------
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First, a DTM config must be created for the system that you want to create.
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This involves specifying the SoC top-level to add a DTM as well as configuring that DTM to use JTAG.
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.. code-block:: scala
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class DTMBoomConfig extends Config(
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new WithDTMBoomRocketTop ++
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new WithBootROM ++
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new WithJtagDTM ++
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new boom.common.SmallBoomConfig)
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In this example, the ``WithDTMBoomRocketTop`` mixin specifies that the top-level SoC will instantiate a DTM.
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The ``WithJtagDTM`` will configure that instantiated DTM to use JTAG as the bringup method (note: this can be removed if you want a DTM-only bringup).
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The rest of the mixins specify the rest of the system (cores, accelerators, etc).
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Starting the DTM Simulation
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-------------------------------------------
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After creating the config, call the ``make`` command like the following:
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.. code-block:: bash
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cd sims/verilator
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# or
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cd sims/vcs
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make CONFIG=DTMBoomConfig TOP=BoomRocketTopWithDTM MODEL=TestHarnessWithDTM
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In this example, this will use the config that you previously specified, as well as set the other parameters that are needed to satisfy the build system.
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After that point, you should have a JTAG enabled simulation that you can attach to using OpenOCD and GDB!
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Debugging with JTAG
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-------------------------------------------------------
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Please refer to the following resources on how to debug with JTAG.
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* https://github.com/chipsalliance/rocket-chip#-debugging-with-gdb
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* https://github.com/riscv/riscv-isa-sim#debugging-with-gdb
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