01238c8b7a
* [docs] rename config mixins -> fragments [ci skip] * [docs] cleanup naming | link similar sections [ci skip] * [boom] bump for mixin rename [ci skip] * [docs] cleanup capitalization [ci skip] * [docs] consistent config fragment naming [ci skip] * [boom] bump boom for documentation changes [ci skip] * [docs] update source comments [ci skip] * [docs] fix last config fragment name [ci skip] Co-Authored-By: alonamid <alonamid@eecs.berkeley.edu> Co-authored-by: alonamid <alonamid@eecs.berkeley.edu>
70 lines
3.6 KiB
ReStructuredText
70 lines
3.6 KiB
ReStructuredText
Tops, Test-Harnesses, and the Test-Driver
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===========================================
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The three highest levels of hierarchy in a Chipyard
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SoC are the Top (DUT), ``TestHarness``, and the ``TestDriver``.
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The Top and ``TestHarness`` are both emitted by Chisel generators.
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The ``TestDriver`` serves as our testbench, and is a Verilog
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file in Rocket Chip.
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Top/DUT
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-------------------------
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The top-level module of a Rocket Chip SoC is composed via cake-pattern.
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Specifically, "Tops" extend a ``System``, which extends a ``Subsystem``, which extends a ``BaseSubsystem``.
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BaseSubsystem
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^^^^^^^^^^^^^^^^^^^^^^^^^
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The ``BaseSubsystem`` is defined in ``generators/rocketchip/src/main/scala/subsystem/BaseSubsystem.scala``.
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Looking at the ``BaseSubsystem`` abstract class, we see that this class instantiates the top-level buses
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(frontbus, systembus, peripherybus, etc.), but does not specify a topology.
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We also see this class define several ``ElaborationArtefacts``, files emitted after Chisel elaboration
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(e.g. the device tree string, and the diplomacy graph visualization GraphML file).
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Subsystem
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^^^^^^^^^^^^^^^^^^^^^^^^^
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Looking in `generators/chipyard/src/main/scala/Subsystem.scala <https://github.com/ucb-bar/chipyard/blob/master/generators/chipyard/src/main/scala/Subsystem.scala>`__, we can see how Chipyard's ``Subsystem``
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extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that
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defines and instantiates BOOM or Rocket tiles, depending on the parameters specified.
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We also connect some basic IOs for each tile here, specifically the hartids and the reset vector.
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System
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^^^^^^^^^^^^^^^^^^^^^^^^^
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``generators/chipyard/src/main/scala/System.scala`` completes the definition of the ``System``.
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- ``HasHierarchicalBusTopology`` is defined in Rocket Chip, and specifies connections between the top-level buses
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- ``HasAsyncExtInterrupts`` and ``HasExtInterruptsModuleImp`` adds IOs for external interrupts and wires them appropriately to tiles
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- ``CanHave...AXI4Port`` adds various Master and Slave AXI4 ports, adds TL-to-AXI4 converters, and connects them to the appropriate buses
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- ``HasPeripheryBootROM`` adds a BootROM device
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Tops
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^^^^^^^^^^^^^^^^^^^^^^^^^
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A SoC Top then extends the ``System`` class with traits for custom components.
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In Chipyard, this includes things like adding a NIC, UART, and GPIO as well as setting up the hardware for the bringup method.
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Please refer to :ref:`Communicating with the DUT` for more information on these bringup methods.
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TestHarness
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-------------------------
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The wiring between the ``TestHarness`` and the Top are performed in methods defined in traits added to the Top.
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When these methods are called from the ``TestHarness``, they may instantiate modules within the scope of the harness,
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and then connect them to the DUT. For example, the ``connectSimAXIMem`` method defined in the
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``CanHaveMasterAXI4MemPortModuleImp`` trait, when called from the ``TestHarness``, will instantiate ``SimAXIMems``
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and connect them to the correct IOs of the top.
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While this roundabout way of attaching to the IOs of the top may seem to be unnecessarily complex, it allows the designer to compose
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custom traits together without having to worry about the details of the implementation of any particular trait.
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TestDriver
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-------------------------
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The ``TestDriver`` is defined in ``generators/rocketchip/src/main/resources/vsrc/TestDriver.v``.
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This Verilog file executes a simulation by instantiating the ``TestHarness``, driving the clock and reset signals, and interpreting the success output.
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This file is compiled with the generated Verilog for the ``TestHarness`` and the ``Top`` to produce a simulator.
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