52 lines
1.7 KiB
Scala
52 lines
1.7 KiB
Scala
package chipyard.fpga.vcu118.bringup
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import chisel3._
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import chisel3.experimental.{Analog, IO, BaseModule}
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import freechips.rocketchip.util.{HeterogeneousBag}
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import freechips.rocketchip.tilelink.{TLBundle}
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import sifive.blocks.devices.uart.{HasPeripheryUARTModuleImp, UARTPortIO}
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import sifive.blocks.devices.spi.{HasPeripherySPI, SPIPortIO}
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import sifive.blocks.devices.i2c.{HasPeripheryI2CModuleImp, I2CPort}
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import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp, GPIOPortIO}
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import testchipip.{HasPeripheryTSIHostWidget, TSIHostWidgetIO}
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import chipyard.harness._
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import chipyard.iobinders._
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/*** UART ***/
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class WithBringupUART extends HarnessBinder({
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case (th: BringupVCU118FPGATestHarnessImp, port: UARTPort) => {
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th.bringupOuter.io_fmc_uart_bb.bundle <> port.io
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}
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})
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/*** I2C ***/
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class WithBringupI2C extends HarnessBinder({
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case (th: BringupVCU118FPGATestHarnessImp, port: chipyard.iobinders.I2CPort) => {
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th.bringupOuter.io_i2c_bb.bundle <> port.io
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}
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})
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/*** GPIO ***/
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class WithBringupGPIO extends HarnessBinder({
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case (th: BringupVCU118FPGATestHarnessImp, port: GPIOPort) => {
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th.bringupOuter.io_gpio_bb(port.pinId).bundle <> port.io
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}
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})
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/*** TSI Host Widget ***/
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class WithBringupTSIHost extends HarnessBinder({
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case (th: BringupVCU118FPGATestHarnessImp, port: TLMemPort) => {
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val tsiBundles = th.bringupOuter.tsiDdrClient.out.map(_._1)
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val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
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tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
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tsiDdrClientBundle <> port.io
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}
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case (th: BringupVCU118FPGATestHarnessImp, port: TSIHostWidgetPort) => {
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th.bringupOuter.io_tsi_serial_bb.bundle <> port.io
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}
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})
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