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chipyard/sims/common-sim-flags.mk
abnerhexu ec349a854f
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Add Blackwell tensor core support to Chipyard
- Update RadianceConfigs.scala with Blackwell configurations
- Update Verilator Makefile with optimized build flags
- Update submodules: radiance (Blackwell implementation), gemmini (params update)
- Update build flags and gitignore
2026-05-06 14:52:08 +08:00

43 lines
1022 B
Makefile

#----------------------------------------------------------------------------------------
# common gcc configuration/optimization
#----------------------------------------------------------------------------------------
SIM_OPT_CXXFLAGS := -O0
LRISCV=-lriscv
export USE_CHISEL6=1
SIM_CXXFLAGS = \
$(CXXFLAGS) \
$(SIM_OPT_CXXFLAGS) \
-std=c++17 \
-I$(RISCV)/include \
-I$(dramsim_dir) \
-I$(GEN_COLLATERAL_DIR) \
$(EXTRA_SIM_CXXFLAGS)
SIM_LDFLAGS = \
$(LDFLAGS) \
-L$(RISCV)/lib \
-Wl,-rpath,$(RISCV)/lib \
-L$(sim_dir) \
-L$(dramsim_dir) \
$(LRISCV) \
-lfesvr \
-ldramsim \
$(EXTRA_SIM_LDFLAGS)
CLOCK_PERIOD ?= 1.0
RESET_DELAY ?= 777.7
SIM_PREPROC_DEFINES = \
+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
+define+RESET_DELAY=$(RESET_DELAY) \
+define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \
+define+MODEL=$(MODEL) \
+define+RANDOMIZE_MEM_INIT \
+define+RANDOMIZE_REG_INIT \
+define+RANDOMIZE_GARBAGE_ASSIGN \
+define+RANDOMIZE_INVALID_ASSIGN \
$(EXTRA_SIM_PREPROC_DEFINES)