Jerry Zhao 39092e9b00 Switch RTL-sim/FPGA/VLSI flows to chisel6

2024-05-13 12:48:06 -07:00

..

firesim @ c011746410

Bump firesim to version with detached build.sbt

2024-04-25 12:16:43 -07:00

vcs

Pass -top flag to VCS to avoid simulating non-tops

2024-03-19 23:49:08 -07:00

verilator

Add incdirs to vcs/verilator flows

2024-03-19 23:48:51 -07:00

xcelium

Enable precommit | Format files

2023-08-28 14:56:55 -07:00

common-sim-flags.mk

Switch RTL-sim/FPGA/VLSI flows to chisel6

2024-05-13 12:48:06 -07:00