40 lines
1.9 KiB
ReStructuredText
40 lines
1.9 KiB
ReStructuredText
Accessing Scala Resources
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===============================
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A simple way to copy over a source file to the build directory to be used for a simulation compile or VLSI flow is to use the ``addResource`` function given by FIRRTL.
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An example of its use can be seen in `generators/testchipip/src/main/scala/SimTSI.scala <https://github.com/ucb-bar/testchipip/blob/master/src/main/scala/SimTSI.scala>`_.
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Here is the example inlined:
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.. code-block:: scala
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class SimTSI extends BlackBox with HasBlackBoxResource {
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val io = IO(new Bundle {
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val clock = Input(Clock())
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val reset = Input(Bool())
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val tsi = Flipped(new TSIIO)
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val exit = Output(Bool())
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})
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addResource("/testchipip/vsrc/SimTSI.v")
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addResource("/testchipip/csrc/SimTSI.cc")
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}
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In this example, the ``SimTSI`` files will be copied from a specific folder (in this case the ``path/to/testchipip/src/main/resources/testchipip/...``) to the build folder.
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The ``addResource`` path retrieves resources from the ``src/main/resources`` directory.
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So to get an item at ``src/main/resources/fileA.v`` you can use ``addResource("/fileA.v")``.
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However, one caveat of this approach is that to retrieve the file during the FIRRTL compile, you must have that project in the FIRRTL compiler's classpath.
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Thus, you need to add the SBT project as a dependency to the FIRRTL compiler in the Chipyard ``build.sbt``, which in Chipyards case is the ``tapeout`` project.
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For example, you added a new project called ``myAwesomeAccel`` in the Chipyard ``build.sbt``.
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Then you can add it as a ``dependsOn`` dependency to the ``tapeout`` project.
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For example:
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.. code-block:: scala
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lazy val myAwesomeAccel = (project in file("generators/myAwesomeAccelFolder"))
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.dependsOn(rocketchip)
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.settings(commonSettings)
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lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
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.dependsOn(myAwesomeAccel)
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.settings(commonSettings)
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