ac5235e5ed
* Refactor how Configs parameterize the Top and TestHarnesses * Bump sha3, testchipip, icenet, firesim
112 lines
4.5 KiB
Scala
112 lines
4.5 KiB
Scala
package example
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import chisel3._
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import freechips.rocketchip.config.{Config}
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// ---------------------
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// BOOM Configs
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// ---------------------
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class SmallBoomConfig extends Config(
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new WithTSI ++ // use testchipip serial offchip link
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new WithNoGPIO ++ // no top-level GPIO pins (overrides default set in sifive-blocks)
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new WithBootROM ++ // use testchipip bootrom
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new WithUART ++ // add a UART
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level mmio master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level mmio slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive L2 cache
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new boom.common.WithSmallBooms ++ // 1-wide BOOM
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new boom.common.WithNBoomCores(1) ++ // single-core
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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class MediumBoomConfig extends Config(
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new WithTSI ++
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new WithNoGPIO ++
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithMediumBooms ++ // 2-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class LargeBoomConfig extends Config(
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new WithTSI ++
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new WithNoGPIO ++
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithLargeBooms ++ // 3-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class MegaBoomConfig extends Config(
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new WithTSI ++
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new WithNoGPIO ++
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithMegaBooms ++ // 4-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class DualSmallBoomConfig extends Config(
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new WithTSI ++
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new WithNoGPIO ++
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithSmallBooms ++
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new boom.common.WithNBoomCores(2) ++ // dual-core
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new freechips.rocketchip.system.BaseConfig)
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class SmallRV32BoomConfig extends Config(
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new WithTSI ++
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new WithNoGPIO ++
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithoutBoomFPU ++ // no fp
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new boom.common.WithBoomRV32 ++ // rv32 (32bit)
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new boom.common.WithSmallBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class HwachaLargeBoomConfig extends Config(
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new WithTSI ++
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new WithNoGPIO ++
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new hwacha.DefaultHwachaConfig ++ // use Hwacha vector accelerator
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new boom.common.WithLargeBooms ++ // 3-wide BOOM
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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class LoopbackNICBoomConfig extends Config(
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new WithTSI ++
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new WithNoGPIO ++
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new WithLoopbackNIC ++ // loopback the NIC
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new WithIceNIC ++ // add IceNIC
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new WithBootROM ++
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new WithUART ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new boom.common.WithLargeBooms ++
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new boom.common.WithNBoomCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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