56 lines
1.3 KiB
Makefile
56 lines
1.3 KiB
Makefile
base_dir=$(abspath ..)
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sim_dir=$(abspath .)
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PROJECT ?= example
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MODEL ?= TestHarness
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CONFIG ?= DefaultExampleConfig
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CFG_PROJECT ?= $(PROJECT)
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TB ?= TestDriver
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simv = simv-$(PROJECT)-$(CONFIG)
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simv_debug = simv-$(PROJECT)-$(CONFIG)-debug
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default: $(simv)
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debug: $(simv_debug)
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include $(base_dir)/Makefrag
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sim_vsrcs = \
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$(build_dir)/$(PROJECT).$(MODEL).$(CONFIG).v \
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$(base_dir)/testchipip/vsrc/TestDriver.v \
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$(base_dir)/testchipip/vsrc/SimSerial.v
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sim_csrcs = \
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$(base_dir)/testchipip/csrc/SimSerial.cc
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VCS = vcs -full64
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VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1ns/10ps -quiet \
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+rad +v2k +vcs+lic+wait \
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+vc+list -CC "-I$(VCS_HOME)/include" \
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-CC "-I$(RISCV)/include" \
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-CC "-std=c++11" \
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-CC "-Wl,-rpath,$(RISCV)/lib" \
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$(RISCV)/lib/libfesvr.so \
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-sverilog \
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+incdir+$(generated_dir) \
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+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
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+define+PRINTF_COND=$(TB).printf_cond \
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+define+STOP_COND=!$(TB).reset \
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+define+RANDOMIZE_MEM_INIT \
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+define+RANDOMIZE_REG_INIT \
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+define+RANDOMIZE_GARBAGE_ASSIGN \
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+define+RANDOMIZE_INVALID_ASSIGN \
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+libext+.v \
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verilog: $(sim_vsrcs)
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$(simv): $(sim_vsrcs) $(sim_csrcs)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
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-debug_pp
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$(simv_debug) : $(sim_vsrcs) $(sim_csrcs)
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rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
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+define+DEBUG -debug_pp
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