build warnings clean

hw/rtl/VX_config.vh

@@ -202,16 +202,16 @@
 `define DCREQ_SIZE 4
 `endif
 
-// Miss Reserv Queue Knob
-`ifndef DMRVQ_SIZE
-`define DMRVQ_SIZE `MAX(`LSUQ_SIZE, 4)
-`endif
-
 // Core Writeback Queue Size
 `ifndef DCWBQ_SIZE
 `define DCWBQ_SIZE 4
 `endif
 
+// Miss Reserv Queue Knob
+`ifndef DMRVQ_SIZE
+`define DMRVQ_SIZE `MAX(`LSUQ_SIZE, 4)
+`endif
+
 // DRAM Request Queue Size
 `ifndef DDREQ_SIZE
 `define DDREQ_SIZE 4
@@ -244,16 +244,16 @@
 `define ICREQ_SIZE 4
 `endif
 
-// Miss Reserv Queue Knob
-`ifndef IMRVQ_SIZE
-`define IMRVQ_SIZE 4
-`endif
-
 // Core Writeback Queue Size
 `ifndef ICWBQ_SIZE
 `define ICWBQ_SIZE 4
 `endif
 
+// Miss Reserv Queue Knob
+`ifndef IMRVQ_SIZE
+`define IMRVQ_SIZE 4
+`endif
+
 // DRAM Request Queue Size
 `ifndef IDREQ_SIZE
 `define IDREQ_SIZE 4
@@ -303,16 +303,16 @@
 `define L2CREQ_SIZE 4
 `endif
 
-// Miss Reserv Queue Knob
-`ifndef L2MRVQ_SIZE
-`define L2MRVQ_SIZE 8
-`endif
-
 // Core Writeback Queue Size
 `ifndef L2CWBQ_SIZE
 `define L2CWBQ_SIZE 4
 `endif
 
+// Miss Reserv Queue Knob
+`ifndef L2MRVQ_SIZE
+`define L2MRVQ_SIZE 8
+`endif
+
 // DRAM Request Queue Size
 `ifndef L2DREQ_SIZE
 `define L2DREQ_SIZE 4
@@ -350,16 +350,16 @@
 `define L3CREQ_SIZE 4
 `endif
 
-// Miss Reserv Queue Knob
-`ifndef L3MRVQ_SIZE
-`define L3MRVQ_SIZE 8
-`endif
-
 // Core Writeback Queue Size
 `ifndef L3CWBQ_SIZE
 `define L3CWBQ_SIZE 4
 `endif
 
+// Miss Reserv Queue Knob
+`ifndef L3MRVQ_SIZE
+`define L3MRVQ_SIZE 8
+`endif
+
 // DRAM Request Queue Size
 `ifndef L3DREQ_SIZE
 `define L3DREQ_SIZE 4