diff --git a/rtl/Makefile b/rtl/Makefile index 96ba4c26..15df9944 100644 --- a/rtl/Makefile +++ b/rtl/Makefile @@ -9,4 +9,9 @@ VERILATOR: RUNFILE: VERILATOR (cd obj_dir && make -j -f Vvortex.mk) + + + +clean: + rm ./obj_dir/* diff --git a/rtl/VX_decode.v b/rtl/VX_decode.v index 068a40bb..9b974ece 100644 --- a/rtl/VX_decode.v +++ b/rtl/VX_decode.v @@ -96,6 +96,11 @@ module VX_decode( wire[1:0] csr_type; reg[3:0] csr_alu; + + // always @(posedge clk) begin + // $display("Decode: curr_pc: %h", in_curr_PC); + // end + VX_register_file vx_register_file( .clk(clk), .in_write_register(write_register), @@ -142,8 +147,13 @@ module VX_decode( // ch_print("DECODE: PC: {0}, INSTRUCTION: {1}", in_curr_PC, in_instruction); - assign out_rd1 = (is_jal == 1'b1) ? in_curr_PC : - ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register); + assign out_rd1 = ((is_jal == 1'b1) ? in_curr_PC : ((in_src1_fwd == 1'b1) ? in_src1_fwd_data : rd1_register)); + + // always @(negedge clk) begin + // if (in_curr_PC == 32'h800001f0) begin + // $display("IN DECODE: Going to write to: %d with val: %h [%h, %h, %h]", out_rd, out_rd1, in_curr_PC, in_src1_fwd_data, rd1_register); + // end + // end assign out_rd2 = (in_src2_fwd == 1'b1) ? in_src2_fwd_data : rd2_register; diff --git a/rtl/VX_execute.v b/rtl/VX_execute.v index 79fd6184..30d1957c 100644 --- a/rtl/VX_execute.v +++ b/rtl/VX_execute.v @@ -45,8 +45,6 @@ module VX_execute ( output wire out_valid ); - - wire which_in2; wire[31:0] ALU_in1; @@ -66,6 +64,10 @@ module VX_execute ( assign out_jal = in_jal; + // always @(*) begin + // $display("EXECUTE CURR_PC: %h",in_curr_PC); + // end + always @(*) begin case(in_alu_op) `ADD: @@ -76,11 +78,12 @@ module VX_execute ( `SUB: begin out_alu_result = $signed(ALU_in1) - $signed(ALU_in2); + // $display("PC: %h ----> %h and %h",in_curr_PC, $signed(ALU_in1), $signed(ALU_in2)); out_csr_result = 32'hdeadbeef; end `SLLA: begin - out_alu_result = ALU_in1 << ALU_in2; + out_alu_result = ALU_in1 << ALU_in2[4:0]; out_csr_result = 32'hdeadbeef; end `SLT: @@ -101,12 +104,13 @@ module VX_execute ( end `SRL: begin - out_alu_result = ALU_in1 >> ALU_in2; + out_alu_result = ALU_in1 >> ALU_in2[4:0]; out_csr_result = 32'hdeadbeef; end `SRA: begin - out_alu_result = $signed(ALU_in1) >> ALU_in2; + out_alu_result = $signed(ALU_in1) >>> ALU_in2[4:0]; + // $display("Shifting right arithmatic - PC: %h\t%h >>> %h = %h",in_curr_PC, $signed(ALU_in1), ALU_in2, out_alu_result); out_csr_result = 32'hdeadbeef; end `OR: diff --git a/rtl/VX_f_d_reg.v b/rtl/VX_f_d_reg.v index ba0ef7f3..8585ce85 100644 --- a/rtl/VX_f_d_reg.v +++ b/rtl/VX_f_d_reg.v @@ -24,10 +24,12 @@ module VX_f_d_reg ( always @(posedge clk or posedge reset) begin - if(reset || (in_fwd_stall == 1'b1) || (in_freeze == 1'b1)) begin + if(reset) begin instruction <= 32'h0; curr_PC <= 32'h0; valid <= 1'b0; + end else if (in_fwd_stall == 1'b1 || in_freeze == 1'b1) begin + // $display("Because of FWD stall keeping pc: %h", curr_PC); end else begin instruction <= in_instruction; valid <= in_valid; @@ -35,6 +37,9 @@ module VX_f_d_reg ( end end + always @(*) begin + // $display("PC in VX_f_d_reg: %h", curr_PC); + end assign out_instruction = instruction; assign out_curr_PC = curr_PC; diff --git a/rtl/VX_fetch.v b/rtl/VX_fetch.v index 7bf3a35b..7bfb0dcb 100644 --- a/rtl/VX_fetch.v +++ b/rtl/VX_fetch.v @@ -70,6 +70,7 @@ module VX_fetch ( always @(*) begin if ((delay_reg == 1'b1) && (in_freeze == 1'b0)) begin + // $display("Using old cuz delay: PC: %h",old); PC_to_use = old; end else if (in_debug == 1'b1) begin if (prev_debug == 1'b1) begin @@ -78,12 +79,12 @@ module VX_fetch ( PC_to_use = real_PC; end end else if (stall_reg == 1'b1) begin + // $display("Using old cuz stall: PC: %h\treal_pc: %h",old, real_PC); PC_to_use = old; end else begin PC_to_use = PC_to_use_temp; end end - assign stall = in_branch_stall || in_fwd_stall || in_branch_stall_exe || in_interrupt || delay || in_freeze; @@ -160,7 +161,9 @@ module VX_fetch ( end - + // always @(*) begin + // $display("Fetch out pc: %h", out_PC); + // end diff --git a/rtl/VX_forwarding.v b/rtl/VX_forwarding.v index cc359965..ff904645 100644 --- a/rtl/VX_forwarding.v +++ b/rtl/VX_forwarding.v @@ -125,9 +125,14 @@ module VX_forwarding ( assign out_csr_fwd = csr_exe_fwd || csr_mem_fwd; // COMMENT + wire exe_mem_read_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL; + wire mem_mem_read_stall = ((src1_mem_fwd || src2_mem_fwd) && mem_mem_read) ? `STALL : `NO_STALL; - assign out_fwd_stall = ((src1_exe_fwd || src2_exe_fwd) && exe_mem_read) ? `STALL : `NO_STALL; + assign out_fwd_stall = exe_mem_read_stall || mem_mem_read_stall; + // always @(*) begin + // if (out_fwd_stall) $display("FWD STALL"); + // end assign out_src1_fwd_data = src1_exe_fwd ? ((exe_jal) ? in_execute_PC_next : in_execute_alu_result) : (src1_mem_fwd) ? ((mem_jal) ? in_memory_PC_next : (mem_mem_read ? in_memory_mem_data : in_memory_alu_result)) : diff --git a/rtl/VX_memory.v b/rtl/VX_memory.v index 1ce464f8..06de357f 100644 --- a/rtl/VX_memory.v +++ b/rtl/VX_memory.v @@ -35,6 +35,12 @@ module VX_memory ( output wire[31:0] out_cache_driver_in_data ); + always @(in_mem_read, in_cache_driver_out_data) begin + if (in_mem_read == `LW_MEM_READ) begin + // $display("PC: %h ----> Received: %h", in_curr_PC, in_cache_driver_out_data); + end + end + assign out_delay = 1'b0; assign out_cache_driver_in_address = in_alu_result; @@ -60,7 +66,11 @@ module VX_memory ( always @(*) begin case(in_branch_type) `BEQ: out_branch_dir = (in_alu_result == 0) ? `TAKEN : `NOT_TAKEN; - `BNE: out_branch_dir = (in_alu_result == 0) ? `NOT_TAKEN : `TAKEN; + `BNE: + begin + out_branch_dir = (in_alu_result == 0) ? `NOT_TAKEN : `TAKEN; + // $display("Branch @%h is: %h", in_curr_PC, out_branch_dir); + end `BLT: out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; `BGT: out_branch_dir = (in_alu_result[31] == 0) ? `TAKEN : `NOT_TAKEN; `BLTU: out_branch_dir = (in_alu_result[31] == 0) ? `NOT_TAKEN : `TAKEN; diff --git a/rtl/VX_register_file.v b/rtl/VX_register_file.v index 0754d172..ca7e8bf1 100644 --- a/rtl/VX_register_file.v +++ b/rtl/VX_register_file.v @@ -8,8 +8,8 @@ module VX_register_file ( input wire[4:0] in_src1, input wire[4:0] in_src2, - output wire[31:0] out_src1_data, - output wire[31:0] out_src2_data + output reg[31:0] out_src1_data, + output reg[31:0] out_src2_data ); reg[31:0] registers[31:0]; @@ -20,7 +20,12 @@ module VX_register_file ( wire write_enable; - + // reg[5:0] i; + // always @(posedge clk) begin + // for (i = 0; i < 32; i++) begin + // $display("%d: %h",i, registers[i[4:0]]); + // end + // end assign write_data = in_data; assign write_register = in_rd; @@ -29,12 +34,15 @@ module VX_register_file ( always @(posedge clk) begin if(write_enable) begin + // $display("Writing %h to %d",write_data, write_register); registers[write_register] <= write_data; end end - assign out_src1_data = registers[in_src1]; - assign out_src2_data = registers[in_src2]; + always @(negedge clk) begin + out_src1_data <= registers[in_src1]; + out_src2_data <= registers[in_src2]; + end endmodule diff --git a/rtl/VX_writeback.v b/rtl/VX_writeback.v index a92d269f..86f0bd4a 100644 --- a/rtl/VX_writeback.v +++ b/rtl/VX_writeback.v @@ -17,6 +17,12 @@ module VX_writeback ( wire is_jal; wire uses_alu; + // always @(*) begin + // if (in_PC_next == 32'h800001f4 || in_PC_next == 32'h800001f0) begin + + // $display("(%h) WB Data: %h, to register: %d",in_PC_next - 4, in_mem_result, in_rd); + // end + // end assign is_jal = in_wb == `WB_JAL; assign uses_alu = in_wb == `WB_ALU; diff --git a/rtl/obj_dir/Vvortex b/rtl/obj_dir/Vvortex index 1be666ca..81641bcf 100755 Binary files a/rtl/obj_dir/Vvortex and b/rtl/obj_dir/Vvortex differ diff --git a/rtl/obj_dir/Vvortex.cpp b/rtl/obj_dir/Vvortex.cpp index b67fb7a5..90e8fee8 100644 --- a/rtl/obj_dir/Vvortex.cpp +++ b/rtl/obj_dir/Vvortex.cpp @@ -93,28 +93,28 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__1\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__stall_reg = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)); - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__old = ((IData)(vlTOPp->reset) ? 0U : vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC); - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__BR_reg = ((IData)(vlTOPp->reset) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__memory_branch_dest)); - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg = 0U; - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__real_PC = ((IData)(vlTOPp->reset) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use)); - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__state = ((IData)(vlTOPp->reset) ? 0U : @@ -127,13 +127,13 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__1(VVortex__Syms* __restrict vlSymsp) ((IData)(vlTOPp->Vortex__DOT__memory_branch_dir) ? 2U : 0U)))); - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__JAL_reg = ((IData)(vlTOPp->reset) ? 0U : ((IData)(4U) + vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal_dest)); - // ALWAYS at VX_fetch.v:128 + // ALWAYS at VX_fetch.v:129 vlTOPp->Vortex__DOT__vx_fetch__DOT__prev_debug = 0U; // ALWAYS at VX_fetch.v:71 vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use = @@ -230,7 +230,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) __Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0 = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__csr_address; } - // ALWAYS at VX_register_file.v:30 + // ALWAYS at VX_register_file.v:35 if (((0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb)) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)))) { __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0 @@ -250,6 +250,11 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr[__Vdlyvdim0__Vortex__DOT__vx_csr_handler__DOT__csr__v0] = __Vdlyvval__Vortex__DOT__vx_csr_handler__DOT__csr__v0; } + // ALWAYSPOST at VX_register_file.v:38 + if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0) { + vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0] + = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0; + } // ALWAYS at VX_d_e_reg.v:130 vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__branch_type = ((IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling) @@ -401,12 +406,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result)) : 0xdeadbeefU))) - : - vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers - [ - (0x1fU - & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0x14U))])); + : vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register)); vlTOPp->Vortex__DOT__csr_decode_csr_data = ((0xc00U == (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address)) ? (IData)(vlTOPp->Vortex__DOT__vx_csr_handler__DOT__cycle) @@ -429,11 +429,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) : vlTOPp->Vortex__DOT__vx_csr_handler__DOT__csr [vlTOPp->Vortex__DOT__vx_csr_handler__DOT__decode_csr_address])))); - // ALWAYSPOST at VX_register_file.v:32 - if (__Vdlyvset__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0) { - vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers[__Vdlyvdim0__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0] - = __Vdlyvval__Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers__v0; - } // ALWAYS at VX_e_m_reg.v:117 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__valid = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid; vlTOPp->Vortex__DOT__execute_branch_stall = ((0U @@ -573,7 +568,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__PC_next = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__PC_next_out; // ALWAYS at VX_e_m_reg.v:117 vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb = vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb; - // ALWAYS at VX_execute.v:69 + // ALWAYS at VX_execute.v:71 vlTOPp->Vortex__DOT__execute_alu_result = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ( @@ -625,19 +620,14 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? - ((0x1fU - >= vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 - >> vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - : 0U) + VL_SHIFTRS_III(32,32,5, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)) : - ((0x1fU - >= vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 - >> vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - : 0U)) + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 + >> + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) @@ -660,12 +650,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) ? 1U : 0U) : - ((0x1fU - >= vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 - << vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - : 0U)) + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) @@ -676,7 +664,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 + vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))))); vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; - // ALWAYS at VX_memory.v:60 + // ALWAYS at VX_memory.v:66 vlTOPp->Vortex__DOT__memory_branch_dir = (1U & ((4U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) @@ -765,8 +753,24 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__2(VVortex__Syms* __restrict vlSymsp) : 0U)))); } -void VVortex::_initial__TOP__3(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_initial__TOP__3\n"); ); +VL_INLINE_OPT void VVortex::_sequent__TOP__3(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__3\n"); ); + VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // ALWAYS at VX_register_file.v:42 + vlTOPp->Vortex__DOT__vx_decode__DOT__rd2_register + = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0x14U))]; + // ALWAYS at VX_register_file.v:42 + vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register + = vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers + [(0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU))]; +} + +void VVortex::_initial__TOP__4(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_initial__TOP__4\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body // INITIAL at VX_csr_handler.v:27 @@ -828,8 +832,8 @@ void VVortex::_initial__TOP__3(VVortex__Syms* __restrict vlSymsp) { vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__valid = 0U; } -void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__4\n"); ); +void VVortex::_settle__TOP__5(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_settle__TOP__5\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body vlTOPp->Vortex__DOT__vx_decode__DOT__is_itype = @@ -860,7 +864,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:249 + // ALWAYS at VX_decode.v:259 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -951,7 +955,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { + (vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_offset << 1U)); vlTOPp->out_cache_driver_in_address = vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__alu_result; - // ALWAYS at VX_memory.v:60 + // ALWAYS at VX_memory.v:66 vlTOPp->Vortex__DOT__memory_branch_dir = (1U & ((4U & (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__branch_type)) @@ -1006,7 +1010,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); - // ALWAYS at VX_decode.v:238 + // ALWAYS at VX_decode.v:248 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -1141,7 +1145,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { >> 0x14U))) : 0xdeadbeefU) : 0xdeadbeefU)))))); - // ALWAYS at VX_fetch.v:94 + // ALWAYS at VX_fetch.v:95 vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = ( ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) @@ -1151,7 +1155,7 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) ? vlTOPp->Vortex__DOT__memory_branch_dest : vlTOPp->Vortex__DOT__vx_fetch__DOT__PC_to_use)); - // ALWAYS at VX_execute.v:69 + // ALWAYS at VX_execute.v:71 vlTOPp->Vortex__DOT__execute_alu_result = ((8U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? ( @@ -1203,19 +1207,14 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) ? - ((0x1fU - >= vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 - >> vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - : 0U) + VL_SHIFTRS_III(32,32,5, vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1, + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2)) : - ((0x1fU - >= vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 - >> vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - : 0U)) + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 + >> + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) @@ -1238,12 +1237,10 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { ? 1U : 0U) : - ((0x1fU - >= vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - ? - (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 - << vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2) - : 0U)) + (vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd1 + << + (0x1fU + & vlTOPp->Vortex__DOT__vx_execute__DOT__ALU_in2))) : ((1U & (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__alu_op)) @@ -1260,10 +1257,6 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))); - vlTOPp->Vortex__DOT__forwarding_fwd_stall = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) - & (2U - == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) @@ -1279,6 +1272,22 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd))); + vlTOPp->Vortex__DOT__forwarding_fwd_stall = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + | (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd + = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling = ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); @@ -1297,14 +1306,6 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); - vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd - = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) - & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)))) & (0U - != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); vlTOPp->Vortex__DOT__decode_rd1 = ((0x6fU == (0x7fU & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)) ? vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC @@ -1339,32 +1340,42 @@ void VVortex::_settle__TOP__4(VVortex__Syms* __restrict vlSymsp) { ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result)) : 0xdeadbeefU))) - : vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers - [(0x1fU - & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU))])); + : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register)); } -VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__5\n"); ); +VL_INLINE_OPT void VVortex::_sequent__TOP__6(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_sequent__TOP__6\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body // ALWAYS at VX_f_d_reg.v:26 - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid = (1U - & ((~ - ((IData)(vlTOPp->reset) - | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall)))); + if (vlTOPp->reset) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__valid + = (1U & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall))); + } + } // ALWAYS at VX_f_d_reg.v:26 - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = - (((IData)(vlTOPp->reset) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) - ? 0U : vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC); + if (vlTOPp->reset) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__curr_PC + = vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC; + } + } // ALWAYS at VX_f_d_reg.v:26 - vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - = (((IData)(vlTOPp->reset) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) - ? 0U : ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) - ? 0U : vlTOPp->fe_instruction)); - // ALWAYS at VX_fetch.v:94 + if (vlTOPp->reset) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)))) { + vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + = ((IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__stall) + ? 0U : vlTOPp->fe_instruction); + } + } + // ALWAYS at VX_fetch.v:95 vlTOPp->Vortex__DOT__vx_fetch__DOT__temp_PC = ( ((IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__jal) & (~ (IData)(vlTOPp->Vortex__DOT__vx_fetch__DOT__delay_reg))) @@ -1403,7 +1414,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0x14U) : 0x55U)); - // ALWAYS at VX_decode.v:249 + // ALWAYS at VX_decode.v:259 vlTOPp->Vortex__DOT__decode_branch_type = ((0x63U == (0x7fU @@ -1454,7 +1465,7 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__rd)) & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); - // ALWAYS at VX_decode.v:238 + // ALWAYS at VX_decode.v:248 vlTOPp->Vortex__DOT__decode_itype_immed = ((0x40U & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction) ? ( @@ -1596,10 +1607,6 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) >> 0x14U)))) & (0U != (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))); - vlTOPp->Vortex__DOT__forwarding_fwd_stall = (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) - | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) - & (2U - == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))); vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd = (((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__rd)) @@ -1614,6 +1621,22 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd))) & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd))); + vlTOPp->Vortex__DOT__forwarding_fwd_stall = ((((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_exe_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__wb))) + | (((IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd) + | (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src2_mem_fwd)) + & (2U + == (IData)(vlTOPp->Vortex__DOT__vx_e_m_reg__DOT__wb)))); + vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd + = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) + & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction + >> 0xfU)))) & (0U + != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) + & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); vlTOPp->Vortex__DOT__vx_d_e_reg__DOT__stalling = ((IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); @@ -1632,18 +1655,10 @@ VL_INLINE_OPT void VVortex::_sequent__TOP__5(VVortex__Syms* __restrict vlSymsp) & vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction)))) | (IData)(vlTOPp->Vortex__DOT__forwarding_fwd_stall)) | (IData)(vlTOPp->Vortex__DOT__execute_branch_stall)); - vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_wb_fwd - = ((((((0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)) == (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__rd)) - & (0U != (0x1fU & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU)))) & (0U - != (IData)(vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__wb))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_exe_fwd))) - & (~ (IData)(vlTOPp->Vortex__DOT__vx_forwarding__DOT__src1_mem_fwd))); } -VL_INLINE_OPT void VVortex::_combo__TOP__6(VVortex__Syms* __restrict vlSymsp) { - VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__6\n"); ); +VL_INLINE_OPT void VVortex::_combo__TOP__7(VVortex__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_combo__TOP__7\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body vlTOPp->Vortex__DOT__decode_rd1 = ((0x6fU == (0x7fU @@ -1680,10 +1695,7 @@ VL_INLINE_OPT void VVortex::_combo__TOP__6(VVortex__Syms* __restrict vlSymsp) { ? vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__mem_result : vlTOPp->Vortex__DOT__vx_m_w_reg__DOT__alu_result)) : 0xdeadbeefU))) - : vlTOPp->Vortex__DOT__vx_decode__DOT__vx_register_file__DOT__registers - [(0x1fU - & (vlTOPp->Vortex__DOT__vx_f_d_reg__DOT__instruction - >> 0xfU))])); + : vlTOPp->Vortex__DOT__vx_decode__DOT__rd1_register)); } void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) { @@ -1697,11 +1709,14 @@ void VVortex::_eval(VVortex__Syms* __restrict vlSymsp) { if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { vlTOPp->_sequent__TOP__2(vlSymsp); } + if (((~ (IData)(vlTOPp->clk)) & (IData)(vlTOPp->__Vclklast__TOP__clk))) { + vlTOPp->_sequent__TOP__3(vlSymsp); + } if ((((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk))) | ((IData)(vlTOPp->reset) & (~ (IData)(vlTOPp->__Vclklast__TOP__reset))))) { - vlTOPp->_sequent__TOP__5(vlSymsp); + vlTOPp->_sequent__TOP__6(vlSymsp); } - vlTOPp->_combo__TOP__6(vlSymsp); + vlTOPp->_combo__TOP__7(vlSymsp); // Final vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; @@ -1713,7 +1728,7 @@ void VVortex::_eval_initial(VVortex__Syms* __restrict vlSymsp) { // Body vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; vlTOPp->__Vclklast__TOP__reset = vlTOPp->reset; - vlTOPp->_initial__TOP__3(vlSymsp); + vlTOPp->_initial__TOP__4(vlSymsp); } void VVortex::final() { @@ -1727,7 +1742,7 @@ void VVortex::_eval_settle(VVortex__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVortex::_eval_settle\n"); ); VVortex* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - vlTOPp->_settle__TOP__4(vlSymsp); + vlTOPp->_settle__TOP__5(vlSymsp); } VL_INLINE_OPT QData VVortex::_change_request(VVortex__Syms* __restrict vlSymsp) { @@ -1786,6 +1801,8 @@ void VVortex::_ctor_var_reset() { Vortex__DOT__vx_f_d_reg__DOT__instruction = VL_RAND_RESET_I(32); Vortex__DOT__vx_f_d_reg__DOT__curr_PC = VL_RAND_RESET_I(32); Vortex__DOT__vx_f_d_reg__DOT__valid = VL_RAND_RESET_I(1); + Vortex__DOT__vx_decode__DOT__rd1_register = VL_RAND_RESET_I(32); + Vortex__DOT__vx_decode__DOT__rd2_register = VL_RAND_RESET_I(32); Vortex__DOT__vx_decode__DOT__is_itype = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__is_csr = VL_RAND_RESET_I(1); Vortex__DOT__vx_decode__DOT__alu_tempp = VL_RAND_RESET_I(12); diff --git a/rtl/obj_dir/Vvortex.h b/rtl/obj_dir/Vvortex.h index a839f777..4c184f36 100644 --- a/rtl/obj_dir/Vvortex.h +++ b/rtl/obj_dir/Vvortex.h @@ -94,14 +94,16 @@ VL_MODULE(VVortex) { VL_SIG(Vortex__DOT__vx_fetch__DOT__temp_PC,31,0); VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__instruction,31,0); VL_SIG(Vortex__DOT__vx_f_d_reg__DOT__curr_PC,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__rd1_register,31,0); + VL_SIG(Vortex__DOT__vx_decode__DOT__rd2_register,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd1,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__rd2,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__PC_next_out,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__itype_immed,31,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0); - VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); }; struct { + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__upper_immed,19,0); + VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__csr_mask,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__curr_PC,31,0); VL_SIG(Vortex__DOT__vx_d_e_reg__DOT__jal_offset,31,0); VL_SIG(Vortex__DOT__vx_execute__DOT__ALU_in2,31,0); @@ -159,7 +161,7 @@ VL_MODULE(VVortex) { private: static QData _change_request(VVortex__Syms* __restrict vlSymsp); public: - static void _combo__TOP__6(VVortex__Syms* __restrict vlSymsp); + static void _combo__TOP__7(VVortex__Syms* __restrict vlSymsp); private: void _ctor_var_reset(); public: @@ -171,11 +173,12 @@ VL_MODULE(VVortex) { public: static void _eval_initial(VVortex__Syms* __restrict vlSymsp); static void _eval_settle(VVortex__Syms* __restrict vlSymsp); - static void _initial__TOP__3(VVortex__Syms* __restrict vlSymsp); + static void _initial__TOP__4(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__1(VVortex__Syms* __restrict vlSymsp); static void _sequent__TOP__2(VVortex__Syms* __restrict vlSymsp); - static void _sequent__TOP__5(VVortex__Syms* __restrict vlSymsp); - static void _settle__TOP__4(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__3(VVortex__Syms* __restrict vlSymsp); + static void _sequent__TOP__6(VVortex__Syms* __restrict vlSymsp); + static void _settle__TOP__5(VVortex__Syms* __restrict vlSymsp); } VL_ATTR_ALIGNED(128); #endif // guard diff --git a/rtl/obj_dir/Vvortex__ALL.a b/rtl/obj_dir/Vvortex__ALL.a index ae89e441..8e91e947 100644 Binary files a/rtl/obj_dir/Vvortex__ALL.a and b/rtl/obj_dir/Vvortex__ALL.a differ diff --git a/rtl/obj_dir/Vvortex__verFiles.dat b/rtl/obj_dir/Vvortex__verFiles.dat index c23748c8..5190892b 100644 --- a/rtl/obj_dir/Vvortex__verFiles.dat +++ b/rtl/obj_dir/Vvortex__verFiles.dat @@ -3,23 +3,23 @@ C "-Wall -cc Vortex.v VX_fetch.v VX_f_d_reg.v VX_decode.v VX_register_file.v VX_ S 4608404 12889046060 1553037052 0 1548678579 0 "/usr/local/Cellar/verilator/4.010/bin/verilator_bin" S 1495 12889087229 1553211178 0 1553211178 0 "VX_csr_handler.v" S 4626 12889079539 1553190875 0 1553190875 0 "VX_d_e_reg.v" -S 8412 12889063385 1553211412 0 1553211412 0 "VX_decode.v" +S 8725 12889063385 1553236943 0 1553236943 0 "VX_decode.v" S 1351 12889079483 1553200040 0 1553200040 0 "VX_define.v" S 3644 12889083963 1553196174 0 1553196174 0 "VX_e_m_reg.v" -S 4603 12889081819 1553208546 0 1553208546 0 "VX_execute.v" -S 969 12889050060 1553223828 0 1553223828 0 "VX_f_d_reg.v" -S 3337 12889047675 1553112414 0 1553112414 0 "VX_fetch.v" -S 4771 12889086478 1553200651 0 1553200651 0 "VX_forwarding.v" +S 4919 12889081819 1553236958 0 1553236958 0 "VX_execute.v" +S 1120 12889050060 1553236935 0 1553236935 0 "VX_f_d_reg.v" +S 3537 12889047675 1553236929 0 1553236929 0 "VX_fetch.v" +S 5020 12889086478 1553236985 0 1553236985 0 "VX_forwarding.v" S 1578 12889085814 1553211072 0 1553211072 0 "VX_m_w_reg.v" -S 2315 12889084513 1553197906 0 1553197906 0 "VX_memory.v" -S 726 12889070228 1553188094 0 1553188094 0 "VX_register_file.v" -S 597 12889086287 1553199222 0 1553199222 0 "VX_writeback.v" +S 2606 12889084513 1553234474 0 1553234474 0 "VX_memory.v" +S 958 12889070228 1553234503 0 1553234503 0 "VX_register_file.v" +S 806 12889086287 1553236964 0 1553236964 0 "VX_writeback.v" S 12863 12889050092 1553211358 0 1553211358 0 "Vortex.v" -T 77457 12889096617 1553223839 0 1553223839 0 "obj_dir/VVortex.cpp" -T 7575 12889096616 1553223839 0 1553223839 0 "obj_dir/VVortex.h" -T 1800 12889096619 1553223839 0 1553223839 0 "obj_dir/VVortex.mk" -T 530 12889096615 1553223839 0 1553223839 0 "obj_dir/VVortex__Syms.cpp" -T 711 12889096614 1553223839 0 1553223839 0 "obj_dir/VVortex__Syms.h" -T 455 12889096620 1553223839 0 1553223839 0 "obj_dir/VVortex__ver.d" -T 0 0 1553223839 0 1553223839 0 "obj_dir/VVortex__verFiles.dat" -T 1159 12889096618 1553223839 0 1553223839 0 "obj_dir/VVortex_classes.mk" +T 78272 12889102709 1553237041 0 1553237041 0 "obj_dir/VVortex.cpp" +T 7758 12889102708 1553237041 0 1553237041 0 "obj_dir/VVortex.h" +T 1800 12889102711 1553237041 0 1553237041 0 "obj_dir/VVortex.mk" +T 530 12889102707 1553237041 0 1553237041 0 "obj_dir/VVortex__Syms.cpp" +T 711 12889102706 1553237041 0 1553237041 0 "obj_dir/VVortex__Syms.h" +T 455 12889102712 1553237041 0 1553237041 0 "obj_dir/VVortex__ver.d" +T 0 0 1553237041 0 1553237041 0 "obj_dir/VVortex__verFiles.dat" +T 1159 12889102710 1553237041 0 1553237041 0 "obj_dir/VVortex_classes.mk" diff --git a/rtl/results.txt b/rtl/results.txt index 64c0be96..e11422af 100644 --- a/rtl/results.txt +++ b/rtl/results.txt @@ -5,7 +5,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01843 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-addi.hex **************** @@ -14,7 +14,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03526 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-and.hex **************** @@ -23,7 +23,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01849 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-andi.hex **************** @@ -32,7 +32,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.04472 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-auipc.hex **************** @@ -41,7 +41,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.16923 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-beq.hex **************** @@ -50,7 +50,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02552 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-bge.hex **************** @@ -59,7 +59,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02355 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-bgeu.hex **************** @@ -68,7 +68,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02236 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-blt.hex **************** @@ -77,7 +77,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02552 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-bltu.hex **************** @@ -86,7 +86,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02412 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-bne.hex **************** @@ -95,7 +95,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.02552 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-jal.hex **************** @@ -104,7 +104,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.18033 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-jalr.hex **************** @@ -113,71 +113,62 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.07971 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-lb.hex **************** -# Dynamic Instructions: 135 -# of total cycles: 145 +# Dynamic Instructions: 331 +# of total cycles: 342 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.07407 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 25 +# CPI: 1.03323 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-lbu.hex **************** -# Dynamic Instructions: 135 -# of total cycles: 145 +# Dynamic Instructions: 331 +# of total cycles: 342 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.07407 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 25 +# CPI: 1.03323 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-lh.hex **************** -# Dynamic Instructions: 140 -# of total cycles: 150 +# Dynamic Instructions: 339 +# of total cycles: 350 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.07143 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 25 +# CPI: 1.03245 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-lhu.hex **************** -# Dynamic Instructions: 143 -# of total cycles: 153 +# Dynamic Instructions: 343 +# of total cycles: 354 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.06993 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 25 +# CPI: 1.03207 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-lui.hex **************** -# Dynamic Instructions: 55 -# of total cycles: 65 +# Dynamic Instructions: 73 +# of total cycles: 84 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.18182 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 7 - -**************** ../../src/riscv_tests/rv32ui-p-lui.hex.hex **************** -# Dynamic Instructions: 55 -# of total cycles: 65 -# of forwarding stalls: 0 -# of branch stalls: 0 -# CPI: 1.18182 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 7 +# CPI: 1.15068 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-lw.hex **************** -# Dynamic Instructions: 146 -# of total cycles: 156 +# Dynamic Instructions: 346 +# of total cycles: 357 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.06849 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 25 +# CPI: 1.03179 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-or.hex **************** # Dynamic Instructions: 598 @@ -185,7 +176,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01839 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-ori.hex **************** @@ -194,26 +185,26 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.04348 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sb.hex **************** -# Dynamic Instructions: 161 -# of total cycles: 171 +# Dynamic Instructions: 571 +# of total cycles: 582 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.06211 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 25 +# CPI: 1.01926 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sh.hex **************** -# Dynamic Instructions: 502 -# of total cycles: 512 +# Dynamic Instructions: 603 +# of total cycles: 614 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.01992 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 43 +# CPI: 1.01824 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-simple.hex **************** # Dynamic Instructions: 37 @@ -221,17 +212,17 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.2973 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sll.hex **************** -# Dynamic Instructions: 180 -# of total cycles: 190 +# Dynamic Instructions: 633 +# of total cycles: 644 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.05556 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 35 +# CPI: 1.01738 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-slli.hex **************** # Dynamic Instructions: 311 @@ -239,7 +230,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03537 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-slt.hex **************** @@ -248,7 +239,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01861 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-slti.hex **************** @@ -257,7 +248,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03583 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sltiu.hex **************** @@ -266,7 +257,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03583 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sltu.hex **************** @@ -275,35 +266,35 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01861 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sra.hex **************** -# Dynamic Instructions: 58 -# of total cycles: 68 +# Dynamic Instructions: 654 +# of total cycles: 665 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.17241 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 7 +# CPI: 1.01682 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-srai.hex **************** -# Dynamic Instructions: 56 -# of total cycles: 66 +# Dynamic Instructions: 326 +# of total cycles: 337 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.17857 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 7 +# CPI: 1.03374 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-srl.hex **************** -# Dynamic Instructions: 185 -# of total cycles: 195 +# Dynamic Instructions: 648 +# of total cycles: 659 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.05405 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 35 +# CPI: 1.01698 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-srli.hex **************** # Dynamic Instructions: 320 @@ -311,7 +302,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.03438 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sub.hex **************** @@ -320,17 +311,17 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01874 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-sw.hex **************** -# Dynamic Instructions: 152 -# of total cycles: 162 +# Dynamic Instructions: 612 +# of total cycles: 623 # of forwarding stalls: 0 # of branch stalls: 0 -# CPI: 1.06579 -# time to simulate: 6.95312e-310 milliseconds -# GRADE: Failed on test: 21 +# CPI: 1.01797 +# time to simulate: 6.95313e-310 milliseconds +# GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-xor.hex **************** # Dynamic Instructions: 597 @@ -338,7 +329,7 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.01843 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING **************** ../../src/riscv_tests/rv32ui-p-xori.hex **************** @@ -347,5 +338,5 @@ # of forwarding stalls: 0 # of branch stalls: 0 # CPI: 1.04314 -# time to simulate: 6.95312e-310 milliseconds +# time to simulate: 6.95313e-310 milliseconds # GRADE: PASSING diff --git a/rtl/test_bench.cpp b/rtl/test_bench.cpp index f47d01ff..1feb23a9 100644 --- a/rtl/test_bench.cpp +++ b/rtl/test_bench.cpp @@ -2,7 +2,7 @@ #include "test_bench.h" -#define NUM_TESTS 39 +#define NUM_TESTS 38 int main(int argc, char **argv) { @@ -32,7 +32,6 @@ int main(int argc, char **argv) "../../src/riscv_tests/rv32ui-p-lh.hex", "../../src/riscv_tests/rv32ui-p-lhu.hex", "../../src/riscv_tests/rv32ui-p-lui.hex", - "../../src/riscv_tests/rv32ui-p-lui.hex.hex", "../../src/riscv_tests/rv32ui-p-lw.hex", "../../src/riscv_tests/rv32ui-p-or.hex", "../../src/riscv_tests/rv32ui-p-ori.hex", @@ -60,18 +59,22 @@ int main(int argc, char **argv) { bool curr = v.simulate(tests[ii]); - if ( curr) std::cout << GREEN << "Test Passed: " << tests[ii] << std::endl; - if (!curr) std::cout << RED << "Test Failed: " << tests[ii] << std::endl; + if ( curr) std::cerr << GREEN << "Test Passed: " << tests[ii] << std::endl; + if (!curr) std::cerr << RED << "Test Failed: " << tests[ii] << std::endl; passed = passed && curr; - std::cout << DEFAULT; + std::cerr << DEFAULT; } - if( passed) std::cout << DEFAULT << "PASSED ALL TESTS\n"; - if(!passed) std::cout << DEFAULT << "Failed one or more tests\n"; + if( passed) std::cerr << DEFAULT << "PASSED ALL TESTS\n"; + if(!passed) std::cerr << DEFAULT << "Failed one or more tests\n"; - - // v.simulate("../../src/riscv_tests/rv32ui-p-add.hex"); + + // char testing[] = "../../src/riscv_tests/rv32ui-p-lw.hex"; + + // bool curr = v.simulate(testing); + // if ( curr) std::cerr << GREEN << "Test Passed: " << testing << std::endl; + // if (!curr) std::cerr << RED << "Test Failed: " << testing << std::endl; return 0; diff --git a/rtl/test_bench.h b/rtl/test_bench.h index c6595c2b..b550542c 100644 --- a/rtl/test_bench.h +++ b/rtl/test_bench.h @@ -80,6 +80,53 @@ void Vortex::ProcessFile(void) loadHexImpl(this->instruction_file_name, &this->ram); } +void Vortex::print_stats(bool cycle_test) +{ + + if (cycle_test) + { + this->results << std::left; + // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; + this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; + this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; + this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + else + { + this->results << std::left; + this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; + this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; + } + + + uint32_t status; + ram.getWord(0, &status); + + if (this->unit_test) + { + if (status == 1) + { + this->results << std::setw(24) << "# GRADE:" << "PASSING\n"; + } else + { + this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n"; + } + } + else + { + this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n"; + } + + this->stats_static_inst = 0; + this->stats_dynamic_inst = -1; + this->stats_total_cycles = 0; + this->stats_fwd_stalls = 0; + this->stats_branch_stalls = 0; + +} bool Vortex::ibus_driver() { @@ -166,7 +213,9 @@ bool Vortex::dbus_driver() } else if (vortex->out_cache_driver_in_mem_read == LW_MEM_READ) { - + // printf("Reading mem - Addr: %h = %h\n", addr, data_read); + // std::cout << "Reading mem - Addr: " << std::hex << addr << " = " << data_read << "\n"; + std::cout << std::dec; vortex->in_cache_driver_out_data = data_read; } else if (vortex->out_cache_driver_in_mem_read == LBU_MEM_READ) @@ -222,19 +271,26 @@ bool Vortex::simulate(std::string file_to_simulate) unsigned curr_inst; unsigned new_PC; + + int cycle = 0; while (this->stop && (!(stop && (counter > 5)))) { + // std::cout << "************* Cycle: " << cycle << "\n"; bool istop = ibus_driver(); bool dstop = !dbus_driver(); - stop = istop && dstop; vortex->clk = 1; vortex->eval(); + + vortex->clk = 0; vortex->eval(); + + stop = istop && dstop; + if (stop) { counter++; @@ -243,6 +299,7 @@ bool Vortex::simulate(std::string file_to_simulate) counter = 0; } + cycle++; } uint32_t status; @@ -256,54 +313,6 @@ bool Vortex::simulate(std::string file_to_simulate) } -void Vortex::print_stats(bool cycle_test) -{ - - if (cycle_test) - { - this->results << std::left; - // this->results << "# Static Instructions:\t" << std::dec << this->stats_static_inst << std::endl; - this->results << std::setw(24) << "# Dynamic Instructions:" << std::dec << this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# of forwarding stalls:" << std::dec << this->stats_fwd_stalls << std::endl; - this->results << std::setw(24) << "# of branch stalls:" << std::dec << this->stats_branch_stalls << std::endl; - this->results << std::setw(24) << "# CPI:" << std::dec << (double) this->stats_total_cycles / (double) this->stats_dynamic_inst << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - else - { - this->results << std::left; - this->results << std::setw(24) << "# of total cycles:" << std::dec << this->stats_total_cycles << std::endl; - this->results << std::setw(24) << "# time to simulate: " << std::dec << this->stats_sim_time << " milliseconds" << std::endl; - } - - - uint32_t status; - ram.getWord(0, &status); - - if (this->unit_test) - { - if (status == 1) - { - this->results << std::setw(24) << "# GRADE:" << "PASSING\n"; - } else - { - this->results << std::setw(24) << "# GRADE:" << "Failed on test: " << status << "\n"; - } - } - else - { - this->results << std::setw(24) << "# GRADE:" << "N/A [NOT A UNIT TEST]\n"; - } - - this->stats_static_inst = 0; - this->stats_dynamic_inst = -1; - this->stats_total_cycles = 0; - this->stats_fwd_stalls = 0; - this->stats_branch_stalls = 0; - -} -