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CACHE WORKING just needs lb/sb

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This commit is contained in:
felsabbagh3
2019-10-25 03:03:09 -04:00
parent 1e648c5819
commit 01efe02e8b
19 changed files with 2302 additions and 2358 deletions
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9
rtl/cache/VX_Cache_Bank.v vendored
View File

@@ -90,10 +90,10 @@ module VX_Cache_Bank
assign data_evicted = data_use;
assign eviction_wb = miss && (dirty_use != 1'b0);
assign eviction_wb = (dirty_use != 1'b0) && valid_use;
assign eviction_tag = tag_use;
assign access = (state == CACHE_IDLE) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP) && valid_in;
assign write_from_mem = (state == RECIV_MEM_RSP);
assign readdata = (access) ? data_use[block_offset] : 32'b0; // Fix with actual data
assign hit = (access && (tag_use == o_tag) && valid_use);
//assign eviction_addr = {eviction_tag, actual_index, block_offset, 5'b0}; // Fix with actual data
@@ -104,9 +104,8 @@ module VX_Cache_Bank
wire[`NUM_WORDS_PER_BLOCK-1:0][31:0] data_write;
genvar g;
for (g = 0; g < `NUM_WORDS_PER_BLOCK; g = g + 1) begin
wire correct_block = (block_offset == g);
assign we[g] = (read_or_write && ((access && correct_block) || (write_from_mem && !correct_block)) ) ? 1'b1 : 1'b0;
//assign we[g] = (!(write_from_mem && correct_block) && ((write_from_mem || correct_block) && read_or_write == 1'b1)) ? 1 : 0; // added the "not"
wire normal_write = (read_or_write && ((access && (block_offset == g))) && !miss);
assign we[g] = (normal_write || (write_from_mem)) ? 1'b1 : 1'b0;
assign data_write[g] = write_from_mem ? fetched_writedata[g] : writedata;
end

17
rtl/cache/VX_cache_bank_valid.v vendored
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@@ -7,17 +7,16 @@ module VX_cache_bank_valid
(
input wire [`NT_M1:0] i_p_valid,
input wire [`NT_M1:0][31:0] i_p_addr,
output wire [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
output reg [NUMBER_BANKS - 1 : 0][`NT_M1:0] thread_track_banks
);
genvar t_id;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
wire[2:0] threads_bank = i_p_addr[t_id][4:2];
assign thread_track_banks[threads_bank][t_id] = i_p_valid[t_id];
end
always @(*) begin
thread_track_banks = 0;
for (t_id = 0; t_id <= `NT_M1; t_id = t_id + 1)
begin
thread_track_banks[i_p_addr[t_id][4:2]][t_id] = i_p_valid[t_id];
end
end
endmodule

48
rtl/cache/VX_d_cache.v vendored
View File

@@ -64,9 +64,10 @@ module VX_d_cache(clk,
// Buffer for final data
reg [`NT_M1:0][31:0] final_data_read;
wire[`NT_M1:0][31:0] new_final_data_read;
reg [`NT_M1:0][31:0] new_final_data_read;
wire[`NT_M1:0][31:0] new_final_data_read_Qual;
assign o_p_readdata = final_data_read;
assign o_p_readdata = new_final_data_read_Qual;
@@ -95,6 +96,8 @@ module VX_d_cache(clk,
reg[31:0] miss_addr;
reg[31:0] evict_addr;
wire curr_processor_request_valid = (|i_p_valid);
assign use_valid = (stored_valid == 0) ? i_p_valid : stored_valid;
@@ -121,10 +124,15 @@ module VX_d_cache(clk,
// end
// end
reg[`NT_M1:0] debug_hit_per_bank_mask[NUMBER_BANKS-1:0];
genvar bid;
for (bid = 0; bid < NUMBER_BANKS; bid=bid+1)
begin
wire[`NT_M1:0] use_threads_track_banks = thread_track_banks[bid];
wire[`NT_M1:0] use_threads_track_banks = thread_track_banks[bid];
wire[$clog2(`NT)-1:0] use_thread_index = index_per_bank[bid];
wire use_write_final_data = hit_per_bank[bid];
wire[31:0] use_data_final_data = readdata_per_bank[bid];
VX_priority_encoder_w_mask #(.N(`NT)) choose_thread(
.valids(use_threads_track_banks),
.mask (use_mask_per_bank[bid]),
@@ -132,17 +140,20 @@ module VX_d_cache(clk,
.found (valid_per_bank[bid])
);
assign new_final_data_read[index_per_bank[bid]] = hit_per_bank[bid] ? readdata_per_bank[bid] : 0;
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & {`NT{hit_per_bank[bid]}};
always @(*) begin
if (use_write_final_data) new_final_data_read[use_thread_index] = use_data_final_data;
end
// assign new_final_data_read[use_thread_index] = use_write_final_data ? use_data_final_data : 0;
assign debug_hit_per_bank_mask[bid] = {`NT{hit_per_bank[bid]}};
assign threads_serviced_per_bank[bid] = use_mask_per_bank[bid] & debug_hit_per_bank_mask[bid];
end
// genvar tid;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] | threads_serviced_per_bank[2] | threads_serviced_per_bank[3] | threads_serviced_per_bank[4] | threads_serviced_per_bank[5] | threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
// for(tid = 0; tid )
wire[NUMBER_BANKS - 1 : 0] detect_bank_miss;
assign threads_serviced_Qual = threads_serviced_per_bank[0] | threads_serviced_per_bank[1] |
threads_serviced_per_bank[2] | threads_serviced_per_bank[3] |
threads_serviced_per_bank[4] | threads_serviced_per_bank[5] |
threads_serviced_per_bank[6] | threads_serviced_per_bank[7];
// genvar bbid;
// always @(*) begin
// for (bbid = 0; bbid < NUMBER_BANKS; bbid=bbid+1)
@@ -152,6 +163,14 @@ module VX_d_cache(clk,
// end
genvar tid;
for (tid = 0; tid < `NT; tid =tid+1)
begin
assign new_final_data_read_Qual[tid] = threads_serviced_Qual[tid] ? new_final_data_read[tid] : final_data_read[tid];
end
assign detect_bank_miss = (valid_per_bank & ~hit_per_bank);
wire delay;
@@ -193,10 +212,7 @@ module VX_d_cache(clk,
evict_addr <= eviction_addr_per_bank[miss_bank_index];
end
for (cur_t = 0; cur_t < `NT; cur_t=cur_t+1)
begin
if (threads_serviced_Qual[cur_t]) final_data_read[cur_t] <= new_final_data_read[cur_t];
end
final_data_read <= new_final_data_read_Qual;
end
@@ -245,8 +261,8 @@ module VX_d_cache(clk,
// Mem Rsp
// Req to mem:
assign o_m_evict_addr = evict_addr;
assign o_m_read_addr = miss_addr;
assign o_m_evict_addr = evict_addr & 32'hffffffc0;
assign o_m_read_addr = miss_addr & 32'hffffffc0;
assign o_m_valid = (state == SEND_MEM_REQ);
assign o_m_read_or_write = (state == SEND_MEM_REQ) && (|eviction_wb);
//end