From 062d02ddce64eba97498514051950735b63e76c6 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 4 Mar 2021 20:51:03 -0800 Subject: [PATCH] Merge branch 'master' of https://github.gatech.edu/casl/Vortex --- Flubber_FPGA_Startup_Guide.md | 68 +++++++++++++++++++++++ driver/opae/Makefile | 5 +- driver/opae/vlsim/verilator.vlt | 3 +- driver/opae/vlsim/vortex_afu_shim.sv | 2 +- driver/rtlsim/verilator.vlt | 3 +- hw/rtl/VX_alu_unit.v | 5 +- hw/rtl/VX_core.v | 12 ++-- hw/rtl/VX_decode.v | 3 +- hw/rtl/VX_fpu_unit.v | 2 + hw/rtl/VX_gpr_stage.v | 2 + hw/rtl/VX_gpu_unit.v | 2 + hw/rtl/VX_ibuffer.v | 3 + hw/rtl/VX_icache_stage.v | 2 + hw/rtl/VX_lsu_unit.v | 2 + hw/rtl/VX_mem_unit.v | 28 ++++------ hw/rtl/VX_pipeline.v | 12 ++-- hw/rtl/VX_platform.vh | 4 ++ hw/rtl/VX_warp_sched.v | 3 + hw/rtl/VX_writeback.v | 3 + hw/rtl/afu/vortex_afu.sv | 7 ++- hw/rtl/afu/vortex_afu.vh | 4 ++ hw/rtl/cache/VX_bank.v | 7 +-- hw/rtl/cache/VX_cache.v | 6 +- hw/rtl/cache/VX_data_access.v | 4 ++ hw/rtl/cache/VX_flush_ctrl.v | 4 +- hw/rtl/cache/VX_miss_resrv.v | 6 +- hw/rtl/cache/VX_shared_mem.v | 2 + hw/rtl/cache/VX_tag_access.v | 3 + hw/rtl/interfaces/VX_dcache_core_req_if.v | 7 +-- hw/rtl/interfaces/VX_dcache_core_rsp_if.v | 7 +-- hw/rtl/interfaces/VX_icache_core_req_if.v | 5 +- hw/rtl/interfaces/VX_icache_core_rsp_if.v | 5 +- hw/rtl/libs/VX_dp_ram.v | 1 - hw/rtl/libs/VX_fixed_arbiter.v | 1 + hw/rtl/libs/VX_skid_buffer.v | 3 +- hw/rtl/libs/VX_sp_ram.v | 1 - hw/simulate/verilator.vlt | 3 +- 37 files changed, 163 insertions(+), 77 deletions(-) create mode 100644 Flubber_FPGA_Startup_Guide.md diff --git a/Flubber_FPGA_Startup_Guide.md b/Flubber_FPGA_Startup_Guide.md new file mode 100644 index 00000000..cc908010 --- /dev/null +++ b/Flubber_FPGA_Startup_Guide.md @@ -0,0 +1,68 @@ +# Flubber FPGA Startup and Configuration Guide + +Flubber OPAE setup +------------------ + + $ source /opt/inteldevstack/init_env_user.sh + $ export OPAE_HOME=/opt/opae/1.1.2 + $ export PATH=$OPAE_HOME/bin:$PATH + $ export C_INCLUDE_PATH=$OPAE_HOME/include:$C_INCLUDE_PATH + $ export LIBRARY_PATH=$OPAE_HOME/lib:$LIBRARY_PATH + $ export LD_LIBRARY_PATH=$OPAE_HOME/lib:$LD_LIBRARY_PATH + $ export RISCV_TOOLCHAIN_PATH=/opt/riscv-gnu-toolchain + $ export PATH=:/opt/verilator/bin:$PATH + $ export VERILATOR_ROOT=/opt/verilator + + +Flubber OPAE build +------------------ + +The Flubber FPGA has to following configuration options: +- 1 core fpga (fpga-1c) +- 2 cores fpga (fpga-2c) +- 4 cores fpga (fpga-4c) +- 8 cores fpga (fpga-8c) +- 16 cores fpga (fpga-16c) + $ cd hw/syn/opae + $ make fpga-`# of cores`c +Example: `make fpga-4c` + +A new folder *build_fpga_`# of cores`c* will be created and the build will start and take ~30-45 min to complete. + +Flubber Config Build Progress +----------------------------- + +You could check the last 10 lines in the build log for possible errors until build completion. + $ tail -n 10 ./build_fpga_`# of cores`c/build.log +Example: `tail -n 10 ./build_fpga_4c/build.log` + +Check if the build is still running by looking for quartus_sh, quartus_syn, or quartus_fit programs. + $ ps -u `username` + +If the build fails and you need to restart it, clean up the build folder using the following command: + $ make clean-fpga-`# of cores`c +Example: `make clean-fpga-4c` + +The file `vortex_afu.gbs` should exist when the build is done: + $ ls -lsa ./build_fpga_`# of cores`c/vortex_afu.gbs + +Signing the bitstream and Programming the FPGA +---------------------------------------------- + + $ cd ./build_fpga_`# of cores`c/ + $ PACSign PR -t UPDATE -H openssl_manager -i vortex_afu.gbs -o vortex_afu_unsigned_ssl.gbs + $ fpgasupdate vortex_afu_unsigned_ssl.gbs + +FPGA sample test running OpenCL sgemm kernel +-------------------------------------------- + +Run the following from the Vortex root directory + $ ./ci/blackbox.sh --driver=fpga --app=sgemm --args="-n64" + +Build Script Configuration +-------------------------- + +Inside the ci folder there is a script called `blackbox.sh` which runs different tests on the Vortex processor with different configurations. Run: + $ ./ci/blackbox.sh --help +To see the different configuration options available. +The most important ones are `--driver`, which runs the Vortex test on either the fpga, rtlsim, vlsim, or simx simulators, and `--perf`, which enables the profiling counters for each core. \ No newline at end of file diff --git a/driver/opae/Makefile b/driver/opae/Makefile index 4264c2c0..926d0abf 100644 --- a/driver/opae/Makefile +++ b/driver/opae/Makefile @@ -109,10 +109,7 @@ clean-asesim: clean-vlsim: $(MAKE) -C vlsim clean -clean: - clean-fpga - clean-asesim - clean-vlsim +clean: clean-fpga clean-asesim clean-vlsim ifneq ($(MAKECMDGOALS),clean) -include .depend diff --git a/driver/opae/vlsim/verilator.vlt b/driver/opae/vlsim/verilator.vlt index cb799b65..c7a98916 100644 --- a/driver/opae/vlsim/verilator.vlt +++ b/driver/opae/vlsim/verilator.vlt @@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule UNUSED -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../../hw/rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -rule PINCONNECTEMPTY -file "../../../hw/rtl/fp_cores/fpnew/*" +lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/driver/opae/vlsim/vortex_afu_shim.sv b/driver/opae/vlsim/vortex_afu_shim.sv index cf5735e4..0bcabd03 100644 --- a/driver/opae/vlsim/vortex_afu_shim.sv +++ b/driver/opae/vlsim/vortex_afu_shim.sv @@ -1,5 +1,5 @@ -`include "vortex_afu.vh" `include "VX_define.vh" +`include "vortex_afu.vh" /* verilator lint_off IMPORTSTAR */ import ccip_if_pkg::*; import local_mem_cfg_pkg::*; diff --git a/driver/rtlsim/verilator.vlt b/driver/rtlsim/verilator.vlt index c0cd70d7..792578ea 100644 --- a/driver/rtlsim/verilator.vlt +++ b/driver/rtlsim/verilator.vlt @@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule UNUSED -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../../hw/rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../../hw/rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -rule PINCONNECTEMPTY -file "../../hw/rtl/fp_cores/fpnew/*" +lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 0cab28e2..9751bb48 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -12,7 +12,10 @@ module VX_alu_unit #( // Outputs VX_branch_ctl_if branch_ctl_if, VX_commit_if alu_commit_if -); +); + + `UNUSED_PARAM (CORE_ID) + reg [`NUM_THREADS-1:0][31:0] alu_result; wire [`NUM_THREADS-1:0][31:0] add_result; wire [`NUM_THREADS-1:0][32:0] sub_result; diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 47f23d59..b34b6788 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -73,27 +73,23 @@ module VX_core #( VX_dcache_core_req_if #( .NUM_REQS(`DNUM_REQUESTS), .WORD_SIZE(`DWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_req_if(); VX_dcache_core_rsp_if #( .NUM_REQS(`DNUM_REQUESTS), .WORD_SIZE(`DWORD_SIZE), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_rsp_if(); VX_icache_core_req_if #( .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_req_if(); VX_icache_core_rsp_if #( .WORD_SIZE(`IWORD_SIZE), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_rsp_if(); VX_pipeline #( diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 5e4419da..f68ec116 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -15,9 +15,10 @@ module VX_decode #( VX_wstall_if wstall_if, VX_join_if join_if ); + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (clk) `UNUSED_VAR (reset) - + reg [`EX_BITS-1:0] ex_type; reg [`OP_BITS-1:0] op_type; reg [`MOD_BITS-1:0] op_mod; diff --git a/hw/rtl/VX_fpu_unit.v b/hw/rtl/VX_fpu_unit.v index 1795a489..3b6dd20e 100644 --- a/hw/rtl/VX_fpu_unit.v +++ b/hw/rtl/VX_fpu_unit.v @@ -17,6 +17,8 @@ module VX_fpu_unit #( input wire[`NUM_WARPS-1:0] csr_pending, output wire[`NUM_WARPS-1:0] pending ); + + `UNUSED_PARAM (CORE_ID) localparam FPUQ_BITS = `LOG2UP(`FPUQ_SIZE); wire ready_in; diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 98c07d7c..9367dd75 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -13,6 +13,8 @@ module VX_gpr_stage #( // outputs VX_gpr_rsp_if gpr_rsp_if ); + + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) // ensure r0 never gets written, which can happen before the reset diff --git a/hw/rtl/VX_gpu_unit.v b/hw/rtl/VX_gpu_unit.v index 0c3b1a52..9d0615bb 100644 --- a/hw/rtl/VX_gpu_unit.v +++ b/hw/rtl/VX_gpu_unit.v @@ -15,6 +15,8 @@ module VX_gpu_unit #( VX_warp_ctl_if warp_ctl_if, VX_commit_if gpu_commit_if ); + + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (clk) `UNUSED_VAR (reset) diff --git a/hw/rtl/VX_ibuffer.v b/hw/rtl/VX_ibuffer.v index b4cc2d93..a67c7221 100644 --- a/hw/rtl/VX_ibuffer.v +++ b/hw/rtl/VX_ibuffer.v @@ -13,6 +13,9 @@ module VX_ibuffer #( // outputs VX_decode_if ibuf_deq_if ); + + `UNUSED_PARAM (CORE_ID) + localparam DATAW = `NUM_THREADS + 32 + `EX_BITS + `OP_BITS + `FRM_BITS + 1 + (`NR_BITS * 4) + 32 + 1 + 1 + `NUM_REGS; localparam SIZE = 3; localparam ADDRW = $clog2(SIZE); diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index f30e930a..75688a68 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -18,6 +18,8 @@ module VX_icache_stage #( // reponse VX_ifetch_rsp_if ifetch_rsp_if ); + + `UNUSED_PARAM (CORE_ID) `UNUSED_VAR (reset) wire icache_req_fire = icache_req_if.valid && icache_req_if.ready; diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 2fa7e50a..01a5f00b 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -20,6 +20,8 @@ module VX_lsu_unit #( VX_commit_if st_commit_if ); + `UNUSED_PARAM (CORE_ID) + wire req_valid; wire [`NUM_THREADS-1:0] req_tmask; wire [`NUM_THREADS-1:0][31:0] req_addr; diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 94a30651..9e3b36d1 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -41,31 +41,27 @@ module VX_mem_unit # ( ) dcache_dram_rsp_if(), icache_dram_rsp_if(); VX_dcache_core_req_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) dcache_req_if(); VX_dcache_core_rsp_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) dcache_rsp_if(); VX_dcache_core_req_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) smem_req_if(); VX_dcache_core_rsp_if #( - .NUM_REQS (`DNUM_REQUESTS), - .WORD_SIZE (`DWORD_SIZE), - .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS (`DCORE_TAG_ID_BITS) + .NUM_REQS (`DNUM_REQUESTS), + .WORD_SIZE (`DWORD_SIZE), + .CORE_TAG_WIDTH (`DCORE_TAG_WIDTH) ) smem_rsp_if(); VX_databus_arb databus_arb ( diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 32dd4e64..91305a4f 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -63,8 +63,7 @@ module VX_pipeline #( VX_dcache_core_req_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_req_if(); assign dcache_req_valid = dcache_core_req_if.valid; @@ -82,8 +81,7 @@ module VX_pipeline #( VX_dcache_core_rsp_if #( .NUM_REQS(`NUM_THREADS), .WORD_SIZE(4), - .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`DCORE_TAG_WIDTH) ) dcache_core_rsp_if(); assign dcache_core_rsp_if.valid = dcache_rsp_valid; @@ -97,8 +95,7 @@ module VX_pipeline #( VX_icache_core_req_if #( .WORD_SIZE(4), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_req_if(); assign icache_req_valid = icache_core_req_if.valid; @@ -112,8 +109,7 @@ module VX_pipeline #( VX_icache_core_rsp_if #( .WORD_SIZE(4), - .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH), - .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) + .CORE_TAG_WIDTH(`ICORE_TAG_WIDTH) ) icache_core_rsp_if(); assign icache_core_rsp_if.valid = icache_rsp_valid; diff --git a/hw/rtl/VX_platform.vh b/hw/rtl/VX_platform.vh index 39c605c7..5ec9c74a 100644 --- a/hw/rtl/VX_platform.vh +++ b/hw/rtl/VX_platform.vh @@ -33,6 +33,10 @@ /* verilator lint_on DECLFILENAME */ \ /* verilator lint_on IMPLICIT */ +`define UNUSED_PARAM(x) /* verilator lint_off UNUSED */ \ + localparam __``x = x; \ + /* verilator lint_on UNUSED */ + `define UNUSED_VAR(x) always @(x) begin end `define UNUSED_PIN(x) /* verilator lint_off PINCONNECTEMPTY */ \ diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index a5a1a44c..438ddb0b 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -18,6 +18,9 @@ module VX_warp_sched #( output wire busy ); + + `UNUSED_PARAM (CORE_ID) + wire join_fall; wire [31:0] join_pc; wire [`NUM_THREADS-1:0] join_tm; diff --git a/hw/rtl/VX_writeback.v b/hw/rtl/VX_writeback.v index 27cfb4a0..4dee992f 100644 --- a/hw/rtl/VX_writeback.v +++ b/hw/rtl/VX_writeback.v @@ -15,6 +15,9 @@ module VX_writeback #( // outputs VX_writeback_if writeback_if ); + + `UNUSED_PARAM (CORE_ID) + wire ld_valid = ld_commit_if.valid && ld_commit_if.wb; wire fpu_valid = fpu_commit_if.valid && fpu_commit_if.wb; wire csr_valid = csr_commit_if.valid && csr_commit_if.wb; diff --git a/hw/rtl/afu/vortex_afu.sv b/hw/rtl/afu/vortex_afu.sv index b70541c1..f6c0dc12 100644 --- a/hw/rtl/afu/vortex_afu.sv +++ b/hw/rtl/afu/vortex_afu.sv @@ -1,5 +1,5 @@ +`include "VX_define.vh" `ifndef NOPAE -`include "platform_if.vh" import local_mem_cfg_pkg::*; `include "afu_json_info.vh" `else @@ -10,8 +10,6 @@ import local_mem_cfg_pkg::*; /* verilator lint_on IMPORTSTAR */ `endif -`include "VX_define.vh" - module vortex_afu #( parameter NUM_LOCAL_MEM_BANKS = 2 ) ( @@ -993,6 +991,9 @@ VX_scope #( .bus_write(cmd_scope_write) ); +`else + `UNUSED_PARAM (MMIO_SCOPE_READ) + `UNUSED_PARAM (MMIO_SCOPE_WRITE) `endif endmodule \ No newline at end of file diff --git a/hw/rtl/afu/vortex_afu.vh b/hw/rtl/afu/vortex_afu.vh index 564fd96c..691d488c 100644 --- a/hw/rtl/afu/vortex_afu.vh +++ b/hw/rtl/afu/vortex_afu.vh @@ -1,14 +1,18 @@ `ifndef __VORTEX_AFU__ `define __VORTEX_AFU__ +`IGNORE_WARNINGS_BEGIN `include "ccip_if_pkg.sv" +`IGNORE_WARNINGS_END `define PLATFORM_PROVIDES_LOCAL_MEMORY `define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH 26 `define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH 512 `define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4 +`IGNORE_WARNINGS_BEGIN `include "local_mem_cfg_pkg.sv" +`IGNORE_WARNINGS_END `define AFU_ACCEL_NAME "vortex_afu" `define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 8c889e29..7629b264 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -22,8 +22,6 @@ module VX_bank #( parameter CREQ_SIZE = 1, // Miss Reserv Queue Knob parameter MSHR_SIZE = 1, - // DRAM Response Queue Size - parameter DRSQ_SIZE = 1, // DRAM Request Queue Size parameter DREQ_SIZE = 1, @@ -92,6 +90,8 @@ module VX_bank #( input wire [`LINE_SELECT_BITS-1:0] flush_addr ); + `UNUSED_PARAM (CORE_TAG_ID_BITS) + `ifdef DBG_CACHE_REQ_INFO /* verilator lint_off UNUSED */ wire [31:0] debug_pc_sel, debug_pc_st0, debug_pc_st1; @@ -420,8 +420,7 @@ module VX_bank #( VX_miss_resrv #( .BANK_ID (BANK_ID), - .CACHE_ID (CACHE_ID), - .CORE_TAG_ID_BITS (CORE_TAG_ID_BITS), + .CACHE_ID (CACHE_ID), .CACHE_LINE_SIZE (CACHE_LINE_SIZE), .NUM_BANKS (NUM_BANKS), .NUM_PORTS (NUM_PORTS), diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index 92a1dd39..63133664 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -163,10 +163,9 @@ module VX_cache #( /////////////////////////////////////////////////////////////////////////// VX_flush_ctrl #( - .CACHE_SIZE (CACHE_SIZE), + .CACHE_SIZE (CACHE_SIZE), .CACHE_LINE_SIZE (CACHE_LINE_SIZE), - .NUM_BANKS (NUM_BANKS), - .WORD_SIZE (WORD_SIZE) + .NUM_BANKS (NUM_BANKS) ) flush_ctrl ( .clk (clk), .reset (reset), @@ -294,7 +293,6 @@ module VX_cache #( .NUM_REQS (NUM_REQS), .CREQ_SIZE (CREQ_SIZE), .MSHR_SIZE (MSHR_SIZE), - .DRSQ_SIZE (DRSQ_SIZE), .DREQ_SIZE (DREQ_SIZE), .WRITE_ENABLE (WRITE_ENABLE), .CORE_TAG_WIDTH (CORE_TAG_WIDTH), diff --git a/hw/rtl/cache/VX_data_access.v b/hw/rtl/cache/VX_data_access.v index 01d600a1..fbec1107 100644 --- a/hw/rtl/cache/VX_data_access.v +++ b/hw/rtl/cache/VX_data_access.v @@ -38,6 +38,10 @@ module VX_data_access #( input wire [CACHE_LINE_SIZE-1:0] byteen, input wire [`CACHE_LINE_WIDTH-1:0] wdata ); + + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) + `UNUSED_PARAM (WORD_SIZE) `UNUSED_VAR (reset) `UNUSED_VAR (readen) diff --git a/hw/rtl/cache/VX_flush_ctrl.v b/hw/rtl/cache/VX_flush_ctrl.v index 41926bcc..261197b6 100644 --- a/hw/rtl/cache/VX_flush_ctrl.v +++ b/hw/rtl/cache/VX_flush_ctrl.v @@ -6,9 +6,7 @@ module VX_flush_ctrl #( // Size of line inside a bank in bytes parameter CACHE_LINE_SIZE = 1, // Number of banks - parameter NUM_BANKS = 1, - // Size of a word in bytes - parameter WORD_SIZE = 1 + parameter NUM_BANKS = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/cache/VX_miss_resrv.v b/hw/rtl/cache/VX_miss_resrv.v index fce9e38f..55755d61 100644 --- a/hw/rtl/cache/VX_miss_resrv.v +++ b/hw/rtl/cache/VX_miss_resrv.v @@ -19,9 +19,7 @@ module VX_miss_resrv #( parameter MSHR_SIZE = 1, parameter ALM_FULL = (MSHR_SIZE-1), // core request tag size - parameter CORE_TAG_WIDTH = 1, - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 0 + parameter CORE_TAG_WIDTH = 1 ) ( input wire clk, input wire reset, @@ -58,6 +56,8 @@ module VX_miss_resrv #( // dequeue input wire dequeue ); + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) localparam ADDRW = $clog2(MSHR_SIZE); reg [MSHR_SIZE-1:0][`LINE_ADDR_WIDTH-1:0] addr_table; diff --git a/hw/rtl/cache/VX_shared_mem.v b/hw/rtl/cache/VX_shared_mem.v index 1a768495..4d9eee57 100644 --- a/hw/rtl/cache/VX_shared_mem.v +++ b/hw/rtl/cache/VX_shared_mem.v @@ -49,6 +49,8 @@ module VX_shared_mem #( ); `STATIC_ASSERT(NUM_BANKS <= NUM_REQS, ("invalid value")) + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (CORE_TAG_ID_BITS) localparam CACHE_LINE_SIZE = WORD_SIZE; diff --git a/hw/rtl/cache/VX_tag_access.v b/hw/rtl/cache/VX_tag_access.v index a92f3d12..829f4006 100644 --- a/hw/rtl/cache/VX_tag_access.v +++ b/hw/rtl/cache/VX_tag_access.v @@ -31,6 +31,9 @@ module VX_tag_access #( input wire is_flush, output wire tag_match ); + + `UNUSED_PARAM (CACHE_ID) + `UNUSED_PARAM (BANK_ID) `UNUSED_VAR (reset) `UNUSED_VAR (lookup) diff --git a/hw/rtl/interfaces/VX_dcache_core_req_if.v b/hw/rtl/interfaces/VX_dcache_core_req_if.v index 35a5836e..6fd95087 100644 --- a/hw/rtl/interfaces/VX_dcache_core_req_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_req_if.v @@ -4,10 +4,9 @@ `include "../cache/VX_cache_config.vh" interface VX_dcache_core_req_if #( - parameter NUM_REQS = 1, - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter NUM_REQS = 1, + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire [NUM_REQS-1:0] valid; diff --git a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v index 7f4c5203..6732e455 100644 --- a/hw/rtl/interfaces/VX_dcache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_dcache_core_rsp_if.v @@ -4,10 +4,9 @@ `include "../cache/VX_cache_config.vh" interface VX_dcache_core_rsp_if #( - parameter NUM_REQS = 1, - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter NUM_REQS = 1, + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire [NUM_REQS-1:0] valid; diff --git a/hw/rtl/interfaces/VX_icache_core_req_if.v b/hw/rtl/interfaces/VX_icache_core_req_if.v index a683226a..2edb05d9 100644 --- a/hw/rtl/interfaces/VX_icache_core_req_if.v +++ b/hw/rtl/interfaces/VX_icache_core_req_if.v @@ -4,9 +4,8 @@ `include "../cache/VX_cache_config.vh" interface VX_icache_core_req_if #( - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire valid; diff --git a/hw/rtl/interfaces/VX_icache_core_rsp_if.v b/hw/rtl/interfaces/VX_icache_core_rsp_if.v index e78e1e0b..54ffa56d 100644 --- a/hw/rtl/interfaces/VX_icache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_icache_core_rsp_if.v @@ -4,9 +4,8 @@ `include "../cache/VX_cache_config.vh" interface VX_icache_core_rsp_if #( - parameter WORD_SIZE = 1, - parameter CORE_TAG_WIDTH = 1, - parameter CORE_TAG_ID_BITS = 0 + parameter WORD_SIZE = 1, + parameter CORE_TAG_WIDTH = 1 ) (); wire valid; diff --git a/hw/rtl/libs/VX_dp_ram.v b/hw/rtl/libs/VX_dp_ram.v index ed151ba0..f03788ad 100644 --- a/hw/rtl/libs/VX_dp_ram.v +++ b/hw/rtl/libs/VX_dp_ram.v @@ -8,7 +8,6 @@ module VX_dp_ram #( parameter BUFFERED = 0, parameter RWCHECK = 1, parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), parameter FASTRAM = 0, parameter INITZERO = 0 ) ( diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.v index 5eb13654..6608b7f0 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.v +++ b/hw/rtl/libs/VX_fixed_arbiter.v @@ -14,6 +14,7 @@ module VX_fixed_arbiter #( output wire grant_valid ); + `UNUSED_PARAM (LOCK_ENABLE) `UNUSED_VAR (clk) `UNUSED_VAR (reset) `UNUSED_VAR (enable) diff --git a/hw/rtl/libs/VX_skid_buffer.v b/hw/rtl/libs/VX_skid_buffer.v index c7266c6e..08377cfb 100644 --- a/hw/rtl/libs/VX_skid_buffer.v +++ b/hw/rtl/libs/VX_skid_buffer.v @@ -4,8 +4,7 @@ module VX_skid_buffer #( parameter DATAW = 1, parameter PASSTHRU = 0, parameter NOBACKPRESSURE = 0, - parameter BUFFERED = 0, - parameter FASTRAM = 1 + parameter BUFFERED = 0 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_sp_ram.v b/hw/rtl/libs/VX_sp_ram.v index 7cbf7048..5ed011ec 100644 --- a/hw/rtl/libs/VX_sp_ram.v +++ b/hw/rtl/libs/VX_sp_ram.v @@ -8,7 +8,6 @@ module VX_sp_ram #( parameter BUFFERED = 0, parameter RWCHECK = 1, parameter ADDRW = $clog2(SIZE), - parameter SIZEW = $clog2(SIZE+1), parameter FASTRAM = 0, parameter INITZERO = 0 ) ( diff --git a/hw/simulate/verilator.vlt b/hw/simulate/verilator.vlt index 5598b43e..dd69f119 100644 --- a/hw/simulate/verilator.vlt +++ b/hw/simulate/verilator.vlt @@ -6,4 +6,5 @@ lint_off -rule WIDTH -file "../rtl/fp_cores/fpnew/*" lint_off -rule UNUSED -file "../rtl/fp_cores/fpnew/*" lint_off -rule LITENDIAN -file "../rtl/fp_cores/fpnew/*" lint_off -rule IMPORTSTAR -file "../rtl/fp_cores/fpnew/*" -lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file +lint_off -rule PINCONNECTEMPTY -file "../rtl/fp_cores/fpnew/*" +lint_off -file "../rtl/fp_cores/fpnew/*" \ No newline at end of file