diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/Makefile b/models/memory/cln28hpc/rf2_32x128_wm1/Makefile
new file mode 100644
index 00000000..6eebe0a6
--- /dev/null
+++ b/models/memory/cln28hpc/rf2_32x128_wm1/Makefile
@@ -0,0 +1,12 @@
+all: RUNFILE
+
+# -LDFLAGS '-lsystemc'
+VERILATOR:
+	verilator rf2_32x128_wm1_rtl.v -cc --exe testbench.cpp --Wno-UNOPTFLAT --Wno-WIDTH --Wno-STMTDLY --Wno-UNSIGNED
+
+
+RUNFILE: VERILATOR
+	(cd obj_dir && make -j -f Vrf2_32x128_wm1_rtl.mk)
+
+clean:
+	rm obj_dir/*
\ No newline at end of file
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.cpp b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.cpp
deleted file mode 100644
index f5b7db31..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.cpp
+++ /dev/null
@@ -1,289 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Design implementation internals
-// See Vrf2_32x128_wm1.h for the primary calling header
-
-#include "Vrf2_32x128_wm1.h"
-#include "Vrf2_32x128_wm1__Syms.h"
-
-
-//--------------------
-// STATIC VARIABLES
-
-
-//--------------------
-
-VL_CTOR_IMP(Vrf2_32x128_wm1) {
-    Vrf2_32x128_wm1__Syms* __restrict vlSymsp = __VlSymsp = new Vrf2_32x128_wm1__Syms(this, name());
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Reset internal values
-    
-    // Reset structure values
-    _ctor_var_reset();
-}
-
-void Vrf2_32x128_wm1::__Vconfigure(Vrf2_32x128_wm1__Syms* vlSymsp, bool first) {
-    if (0 && first) {}  // Prevent unused
-    this->__VlSymsp = vlSymsp;
-}
-
-Vrf2_32x128_wm1::~Vrf2_32x128_wm1() {
-    delete __VlSymsp; __VlSymsp=NULL;
-}
-
-//--------------------
-
-
-void Vrf2_32x128_wm1::eval() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vrf2_32x128_wm1::eval\n"); );
-    Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp;  // Setup global symbol table
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-#ifdef VL_DEBUG
-    // Debug assertions
-    _eval_debug_assertions();
-#endif  // VL_DEBUG
-    // Initialize
-    if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp);
-    // Evaluate till stable
-    int __VclockLoop = 0;
-    QData __Vchange = 1;
-    do {
-	VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n"););
-	_eval(vlSymsp);
-	if (VL_UNLIKELY(++__VclockLoop > 100)) {
-	    // About to fail, so enable debug to see what's not settling.
-	    // Note you must run make with OPT=-DVL_DEBUG for debug prints.
-	    int __Vsaved_debug = Verilated::debug();
-	    Verilated::debug(1);
-	    __Vchange = _change_request(vlSymsp);
-	    Verilated::debug(__Vsaved_debug);
-	    VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't converge");
-	} else {
-	    __Vchange = _change_request(vlSymsp);
-	}
-    } while (VL_UNLIKELY(__Vchange));
-}
-
-void Vrf2_32x128_wm1::_eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
-    vlSymsp->__Vm_didInit = true;
-    _eval_initial(vlSymsp);
-    // Evaluate till stable
-    int __VclockLoop = 0;
-    QData __Vchange = 1;
-    do {
-	_eval_settle(vlSymsp);
-	_eval(vlSymsp);
-	if (VL_UNLIKELY(++__VclockLoop > 100)) {
-	    // About to fail, so enable debug to see what's not settling.
-	    // Note you must run make with OPT=-DVL_DEBUG for debug prints.
-	    int __Vsaved_debug = Verilated::debug();
-	    Verilated::debug(1);
-	    __Vchange = _change_request(vlSymsp);
-	    Verilated::debug(__Vsaved_debug);
-	    VL_FATAL_MT(__FILE__,__LINE__,__FILE__,"Verilated model didn't DC converge");
-	} else {
-	    __Vchange = _change_request(vlSymsp);
-	}
-    } while (VL_UNLIKELY(__Vchange));
-}
-
-//--------------------
-// Internal Methods
-
-VL_INLINE_OPT void Vrf2_32x128_wm1::_combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::_combo__TOP__1\n"); );
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    // ALWAYS at rf2_32x128_wm1.v:15356
-    if ((1U & (((~ (IData)(vlTOPp->CEN)) & (~ (IData)(vlTOPp->DFTRAMBYP))) 
-	       & (~ (IData)(vlTOPp->SE))))) {
-	vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 0U;
-	vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = 0U;
-	vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U] 
-	    = vlTOPp->Q_in[0U];
-	vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U] 
-	    = vlTOPp->Q_in[1U];
-	vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U] 
-	    = vlTOPp->Q_in[2U];
-	vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U] 
-	    = vlTOPp->Q_in[3U];
-	while ((1U & (~ (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete)))) {
-	    vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry 
-		= vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_table
-		[(0xfU & vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i)];
-	    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address 
-		= (0xfU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry 
-			   >> 0xdU));
-	    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address 
-		= (1U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry 
-			 >> 0xcU));
-	    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace 
-		= (0x7fU & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry 
-			    >> 5U));
-	    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type 
-		= (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry 
-			 >> 3U));
-	    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault 
-		= (3U & (vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry 
-			 >> 1U));
-	    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid 
-		= (1U & vlTOPp->rf2_32x128_wm1_error_injection__DOT__fault_entry);
-	    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i 
-		= ((IData)(1U) + vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i);
-	    if (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid) {
-		if ((0U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault))) {
-		    if ((((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address) 
-			  == (0xfU & ((IData)(vlTOPp->A) 
-				      >> 1U))) & ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address) 
-						  == 
-						  (1U 
-						   & (IData)(vlTOPp->A))))) {
-			if ((0x40U > (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) {
-			    // Function: bit_error at rf2_32x128_wm1.v:15345
-			    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc 
-				= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace;
-			    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type 
-				= vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type;
-			    vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc) 
-										>> 5U)] 
-				= (((~ ((IData)(1U) 
-					<< (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)))) 
-				    & vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
-				    ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc) 
-				     >> 5U)]) | (((0U 
-						   != (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type)) 
-						  & ((1U 
-						      == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type)) 
-						     | (~ 
-							(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
-							 ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc) 
-							  >> 5U)] 
-							 >> 
-							 (0x1fU 
-							  & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc)))))) 
-						 << 
-						 (0x1fU 
-						  & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc))));
-			} else {
-			    if ((0x40U <= (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace))) {
-				// Function: bit_error at rf2_32x128_wm1.v:15347
-				vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc 
-				    = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace;
-				vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type 
-				    = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type;
-				vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc) 
-										>> 5U)] 
-				    = (((~ ((IData)(1U) 
-					    << (0x1fU 
-						& (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)))) 
-					& vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
-					((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc) 
-					 >> 5U)]) | 
-				       (((0U != (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type)) 
-					 & ((1U == (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type)) 
-					    | (~ (vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[
-						  ((IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc) 
-						   >> 5U)] 
-						  >> 
-						  (0x1fU 
-						   & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc)))))) 
-					<< (0x1fU & (IData)(vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc))));
-			    }
-			}
-		    }
-		}
-	    } else {
-		vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = 1U;
-	    }
-	}
-	vlTOPp->Q_out[0U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[0U];
-	vlTOPp->Q_out[1U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[1U];
-	vlTOPp->Q_out[2U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[2U];
-	vlTOPp->Q_out[3U] = vlTOPp->__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output[3U];
-    } else {
-	vlTOPp->Q_out[0U] = vlTOPp->Q_in[0U];
-	vlTOPp->Q_out[1U] = vlTOPp->Q_in[1U];
-	vlTOPp->Q_out[2U] = vlTOPp->Q_in[2U];
-	vlTOPp->Q_out[3U] = vlTOPp->Q_in[3U];
-    }
-}
-
-void Vrf2_32x128_wm1::_eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::_eval\n"); );
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->_combo__TOP__1(vlSymsp);
-}
-
-void Vrf2_32x128_wm1::_eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::_eval_initial\n"); );
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-}
-
-void Vrf2_32x128_wm1::final() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::final\n"); );
-    // Variables
-    Vrf2_32x128_wm1__Syms* __restrict vlSymsp = this->__VlSymsp;
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-}
-
-void Vrf2_32x128_wm1::_eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::_eval_settle\n"); );
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    vlTOPp->_combo__TOP__1(vlSymsp);
-}
-
-VL_INLINE_OPT QData Vrf2_32x128_wm1::_change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::_change_request\n"); );
-    Vrf2_32x128_wm1* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
-    // Body
-    // Change detection
-    QData __req = false;  // Logically a bool
-    return __req;
-}
-
-#ifdef VL_DEBUG
-void Vrf2_32x128_wm1::_eval_debug_assertions() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::_eval_debug_assertions\n"); );
-    // Body
-    if (VL_UNLIKELY((CLK & 0xfeU))) {
-	Verilated::overWidthError("CLK");}
-    if (VL_UNLIKELY((A & 0xe0U))) {
-	Verilated::overWidthError("A");}
-    if (VL_UNLIKELY((CEN & 0xfeU))) {
-	Verilated::overWidthError("CEN");}
-    if (VL_UNLIKELY((DFTRAMBYP & 0xfeU))) {
-	Verilated::overWidthError("DFTRAMBYP");}
-    if (VL_UNLIKELY((SE & 0xfeU))) {
-	Verilated::overWidthError("SE");}
-}
-#endif // VL_DEBUG
-
-void Vrf2_32x128_wm1::_ctor_var_reset() {
-    VL_DEBUG_IF(VL_DBG_MSGF("+    Vrf2_32x128_wm1::_ctor_var_reset\n"); );
-    // Body
-    VL_RAND_RESET_W(128,Q_out);
-    VL_RAND_RESET_W(128,Q_in);
-    CLK = VL_RAND_RESET_I(1);
-    A = VL_RAND_RESET_I(5);
-    CEN = VL_RAND_RESET_I(1);
-    DFTRAMBYP = VL_RAND_RESET_I(1);
-    SE = VL_RAND_RESET_I(1);
-    { int __Vi0=0; for (; __Vi0<16; ++__Vi0) {
-	    rf2_32x128_wm1_error_injection__DOT__fault_table[__Vi0] = VL_RAND_RESET_I(17);
-    }}
-    rf2_32x128_wm1_error_injection__DOT__fault_entry = VL_RAND_RESET_I(17);
-    VL_RAND_RESET_W(128,__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete = VL_RAND_RESET_I(1);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i = VL_RAND_RESET_I(32);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address = VL_RAND_RESET_I(4);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address = VL_RAND_RESET_I(1);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace = VL_RAND_RESET_I(7);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type = VL_RAND_RESET_I(2);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault = VL_RAND_RESET_I(2);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid = VL_RAND_RESET_I(1);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type = VL_RAND_RESET_I(2);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc = VL_RAND_RESET_I(7);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type = VL_RAND_RESET_I(2);
-    __Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc = VL_RAND_RESET_I(7);
-}
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h
deleted file mode 100644
index c4ae029a..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.h
+++ /dev/null
@@ -1,101 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Primary design header
-//
-// This header should be included by all source files instantiating the design.
-// The class here is then constructed to instantiate the design.
-// See the Verilator manual for examples.
-
-#ifndef _Vrf2_32x128_wm1_H_
-#define _Vrf2_32x128_wm1_H_
-
-#include "verilated.h"
-
-class Vrf2_32x128_wm1__Syms;
-
-//----------
-
-VL_MODULE(Vrf2_32x128_wm1) {
-  public:
-    
-    // PORTS
-    // The application code writes and reads these signals to
-    // propagate new values into/out from the Verilated model.
-    // Begin mtask footprint  all: 
-    VL_IN8(CLK,0,0);
-    VL_IN8(A,4,0);
-    VL_IN8(CEN,0,0);
-    VL_IN8(DFTRAMBYP,0,0);
-    VL_IN8(SE,0,0);
-    VL_OUTW(Q_out,127,0,4);
-    VL_INW(Q_in,127,0,4);
-    
-    // LOCAL SIGNALS
-    // Internals; generally not touched by application code
-    // Begin mtask footprint  all: 
-    VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_entry,16,0);
-    VL_SIG(rf2_32x128_wm1_error_injection__DOT__fault_table[16],16,0);
-    
-    // LOCAL VARIABLES
-    // Internals; generally not touched by application code
-    // Begin mtask footprint  all: 
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__list_complete,0,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__row_address,3,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__column_address,0,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__bitPlace,6,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__fault_type,1,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__red_fault,1,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__valid,0,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__fault_type,1,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__1__bitLoc,6,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__fault_type,1,0);
-    VL_SIG8(__Vtask_rf2_32x128_wm1_error_injection__DOT__bit_error__2__bitLoc,6,0);
-    VL_SIGW(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__Q_output,127,0,4);
-    VL_SIG(__Vtask_rf2_32x128_wm1_error_injection__DOT__error_injection_on_output__0__i,31,0);
-    
-    // INTERNAL VARIABLES
-    // Internals; generally not touched by application code
-    Vrf2_32x128_wm1__Syms* __VlSymsp;  // Symbol table
-    
-    // PARAMETERS
-    // Parameters marked /*verilator public*/ for use by application code
-    
-    // CONSTRUCTORS
-  private:
-    VL_UNCOPYABLE(Vrf2_32x128_wm1);  ///< Copying not allowed
-  public:
-    /// Construct the model; called by application code
-    /// The special name  may be used to make a wrapper with a
-    /// single model invisible with respect to DPI scope names.
-    Vrf2_32x128_wm1(const char* name="TOP");
-    /// Destroy the model; called (often implicitly) by application code
-    ~Vrf2_32x128_wm1();
-    
-    // API METHODS
-    /// Evaluate the model.  Application must call when inputs change.
-    void eval();
-    /// Simulation complete, run final blocks.  Application must call on completion.
-    void final();
-    
-    // INTERNAL METHODS
-  private:
-    static void _eval_initial_loop(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
-  public:
-    void __Vconfigure(Vrf2_32x128_wm1__Syms* symsp, bool first);
-  private:
-    static QData _change_request(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
-  public:
-    static void _combo__TOP__1(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
-  private:
-    void _ctor_var_reset() VL_ATTR_COLD;
-  public:
-    static void _eval(Vrf2_32x128_wm1__Syms* __restrict vlSymsp);
-  private:
-#ifdef VL_DEBUG
-    void _eval_debug_assertions();
-#endif // VL_DEBUG
-  public:
-    static void _eval_initial(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD;
-    static void _eval_settle(Vrf2_32x128_wm1__Syms* __restrict vlSymsp) VL_ATTR_COLD;
-} VL_ATTR_ALIGNED(128);
-
-#endif // guard
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk
deleted file mode 100644
index 2f138e59..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1.mk
+++ /dev/null
@@ -1,53 +0,0 @@
-# Verilated -*- Makefile -*-
-# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
-#
-# Execute this makefile from the object directory:
-#    make -f Vrf2_32x128_wm1.mk
-
-default: Vrf2_32x128_wm1__ALL.a
-
-### Constants...
-# Perl executable (from $PERL)
-PERL = perl
-# Path to Verilator kit (from $VERILATOR_ROOT)
-VERILATOR_ROOT = /usr/local/share/verilator
-# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
-SYSTEMC_INCLUDE ?= 
-# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
-SYSTEMC_LIBDIR ?= 
-
-### Switches...
-# SystemC output mode?  0/1 (from --sc)
-VM_SC = 0
-# Legacy or SystemC output mode?  0/1 (from --sc)
-VM_SP_OR_SC = $(VM_SC)
-# Deprecated
-VM_PCLI = 1
-# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
-VM_SC_TARGET_ARCH = linux
-
-### Vars...
-# Design prefix (from --prefix)
-VM_PREFIX = Vrf2_32x128_wm1
-# Module prefix (from --prefix)
-VM_MODPREFIX = Vrf2_32x128_wm1
-# User CFLAGS (from -CFLAGS on Verilator command line)
-VM_USER_CFLAGS = \
-
-# User LDLIBS (from -LDFLAGS on Verilator command line)
-VM_USER_LDLIBS = \
-
-# User .cpp files (from .cpp's on Verilator command line)
-VM_USER_CLASSES = \
-
-# User .cpp directories (from .cpp's on Verilator command line)
-VM_USER_DIR = \
-
-
-### Default rules...
-# Include list of all generated classes
-include Vrf2_32x128_wm1_classes.mk
-# Include global rules
-include $(VERILATOR_ROOT)/include/verilated.mk
-
-# Verilated -*- Makefile -*-
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp
deleted file mode 100644
index ef09ff5f..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.cpp
+++ /dev/null
@@ -1,19 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Symbol table implementation internals
-
-#include "Vrf2_32x128_wm1__Syms.h"
-#include "Vrf2_32x128_wm1.h"
-
-// FUNCTIONS
-Vrf2_32x128_wm1__Syms::Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep)
-	// Setup locals
-	: __Vm_namep(namep)
-	, __Vm_didInit(false)
-	// Setup submodule names
-{
-    // Pointer to top level
-    TOPp = topp;
-    // Setup each module's pointers to their submodules
-    // Setup each module's pointer back to symbol table (for public functions)
-    TOPp->__Vconfigure(this, true);
-}
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h
deleted file mode 100644
index f77ac3fb..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__Syms.h
+++ /dev/null
@@ -1,35 +0,0 @@
-// Verilated -*- C++ -*-
-// DESCRIPTION: Verilator output: Symbol table internal header
-//
-// Internal details; most calling programs do not need this header,
-// unless using verilator public meta comments.
-
-#ifndef _Vrf2_32x128_wm1__Syms_H_
-#define _Vrf2_32x128_wm1__Syms_H_
-
-#include "verilated.h"
-
-// INCLUDE MODULE CLASSES
-#include "Vrf2_32x128_wm1.h"
-
-// SYMS CLASS
-class Vrf2_32x128_wm1__Syms : public VerilatedSyms {
-  public:
-    
-    // LOCAL STATE
-    const char* __Vm_namep;
-    bool __Vm_didInit;
-    
-    // SUBCELL STATE
-    Vrf2_32x128_wm1*               TOPp;
-    
-    // CREATORS
-    Vrf2_32x128_wm1__Syms(Vrf2_32x128_wm1* topp, const char* namep);
-    ~Vrf2_32x128_wm1__Syms() {}
-    
-    // METHODS
-    inline const char* name() { return __Vm_namep; }
-    
-} VL_ATTR_ALIGNED(64);
-
-#endif  // guard
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d
deleted file mode 100644
index 00d3baae..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__ver.d
+++ /dev/null
@@ -1 +0,0 @@
-obj_dir/Vrf2_32x128_wm1.cpp obj_dir/Vrf2_32x128_wm1.h obj_dir/Vrf2_32x128_wm1.mk obj_dir/Vrf2_32x128_wm1__Syms.cpp obj_dir/Vrf2_32x128_wm1__Syms.h obj_dir/Vrf2_32x128_wm1__ver.d obj_dir/Vrf2_32x128_wm1_classes.mk  : /usr/local/bin/verilator_bin /usr/local/bin/verilator_bin rf2_32x128_wm1.v 
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat
deleted file mode 100644
index 925e8fe6..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1__verFiles.dat
+++ /dev/null
@@ -1,12 +0,0 @@
-# DESCRIPTION: Verilator output: Timestamp data for --skip-identical.  Delete at will.
-C "-cc rf2_32x128_wm1.v"
-S   6746612 12892413243  1567548409           0  1567548409           0 "/usr/local/bin/verilator_bin"
-T     14325  1013347  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1.cpp"
-T      4125  1013346  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1.h"
-T      1478  1013349  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1.mk"
-T       570  1013345  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1__Syms.cpp"
-T       817  1013344  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1__Syms.h"
-T       292  1013350  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1__ver.d"
-T         0        0  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1__verFiles.dat"
-T      1269  1013348  1571096194           0  1571096194           0 "obj_dir/Vrf2_32x128_wm1_classes.mk"
-S   1252191  1011852  1571096122           0  1571096122           0 "rf2_32x128_wm1.v"
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk b/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk
deleted file mode 100644
index a8a44681..00000000
--- a/models/memory/cln28hpc/rf2_32x128_wm1/obj_dir/Vrf2_32x128_wm1_classes.mk
+++ /dev/null
@@ -1,40 +0,0 @@
-# Verilated -*- Makefile -*-
-# DESCRIPTION: Verilator output: Make include file with class lists
-#
-# This file lists generated Verilated files, for including in higher level makefiles.
-# See Vrf2_32x128_wm1.mk for the caller.
-
-### Switches...
-# Coverage output mode?  0/1 (from --coverage)
-VM_COVERAGE = 0
-# Threaded output mode?  0/1/N threads (from --threads)
-VM_THREADS = 0
-# Tracing output mode?  0/1 (from --trace)
-VM_TRACE = 0
-# Tracing threadeds output mode?  0/1 (from --trace-fst-thread)
-VM_TRACE_THREADED = 0
-
-### Object file lists...
-# Generated module classes, fast-path, compile with highest optimization
-VM_CLASSES_FAST += \
-	Vrf2_32x128_wm1 \
-
-# Generated module classes, non-fast-path, compile with low/medium optimization
-VM_CLASSES_SLOW += \
-
-# Generated support classes, fast-path, compile with highest optimization
-VM_SUPPORT_FAST += \
-
-# Generated support classes, non-fast-path, compile with low/medium optimization
-VM_SUPPORT_SLOW += \
-	Vrf2_32x128_wm1__Syms \
-
-# Global classes, need linked once per executable, fast-path, compile with highest optimization
-VM_GLOBAL_FAST += \
-	verilated \
-
-# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
-VM_GLOBAL_SLOW += \
-
-
-# Verilated -*- Makefile -*-
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v b/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
index aefa3087..7cce22f4 100644
--- a/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
+++ b/models/memory/cln28hpc/rf2_32x128_wm1/rf2_32x128_wm1.v
@@ -28,10 +28,10 @@
 //       Power Gating:               Off
 //       Retention:                  On
 //       Pipeline:                   Off
-//       Read Disturb Test:	        Off
+//       Read Disturb Test:         Off
 //       
 //       Creation Date:  Mon Oct 14 17:01:43 2019
-//       Version: 	r0p0
+//       Version:   r0p0
 //
 //      Modeling Assumptions: This model supports full gate level simulation
 //          including proper x-handling and timing check behavior.  Unit
@@ -56,18 +56,12 @@
 `define ARM_MEM_HOLD 0.500
 `define ARM_MEM_COLLISION 3.000
 
-`define REALTIME 1
-
-`undef POWER_PINS
-`undef ARM_MESSAGES
-/* verilator lint_off UNUSED */
-
 module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ,Q);
-	input CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ;
-	output Q;
+  input CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ;
+  output Q;
 
-	reg    D_int;
-	reg    Q;
+  reg    D_int;
+  reg    Q;
 
    //  Model PHI2 portion
    always @(CLK or SE or SI or D) begin
@@ -83,7 +77,7 @@ module datapath_latch_rf2_32x128_wm1 (CLK,Q_update,SE,SI,D,DFTRAMBYP,mem_path,XQ
 
    // model output side of RAM latch
    always @(posedge Q_update or posedge XQ) begin
-      //#0;
+      #0;
       if (XQ===1'b0) begin
          if (DFTRAMBYP===1'b1)
            Q=D_int;
@@ -103,7 +97,7 @@ endmodule // datapath_latch_rf2_32x128_wm1
 // ARM_UD_DP Defines the delay through Data Paths, for Memory Models it represents BIST MUX output delays.
 `ifdef ARM_UD_DP
 `else
-`define ARM_UD_DP //#0.001
+`define ARM_UD_DP #0.001
 `endif
 // ARM_UD_CP Defines the delay through Clock Path Cells, for Memory Models it is not used.
 `ifdef ARM_UD_CP
@@ -113,7 +107,7 @@ endmodule // datapath_latch_rf2_32x128_wm1
 // ARM_UD_SEQ Defines the delay through the Memory, for Memory Models it is used for CLK->Q delays.
 `ifdef ARM_UD_SEQ
 `else
-`define ARM_UD_SEQ //#0.01
+`define ARM_UD_SEQ #0.01
 `endif
 
 `celldefine
@@ -1131,23 +1125,23 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
 `ifdef INITIALIZE_MEMORY
   integer i;
   initial begin
-    //#0;
+    #0;
     for (i = 0; i < MEM_HEIGHT; i = i + 1)
       mem[i] = {MEM_WIDTH{1'b0}};
   end
 `endif
-  // always @ (EMAA_) begin
-  // 	if(EMAA_ < 3) 
-  //  	//$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", 0);
-  // end
-  // always @ (EMASA_) begin
-  // 	if(EMASA_ < 0) 
-  //  	//$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", 0);
-  // end
-  // always @ (EMAB_) begin
-  // 	if(EMAB_ < 3) 
-  //  	//$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", 0);
-  // end
+  always @ (EMAA_) begin
+    if(EMAA_ < 3) 
+    $display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", $time);
+  end
+  always @ (EMASA_) begin
+    if(EMASA_ < 0) 
+    $display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", $time);
+  end
+  always @ (EMAB_) begin
+    if(EMAB_ < 3) 
+    $display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", $time);
+  end
 
   task failedWrite;
   input port_f;
@@ -1174,18 +1168,18 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
 
 
 task loadmem;
-	input [1000*8-1:0] filename;
-	reg [BITS-1:0] memld [0:WORDS-1];
-	integer i;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  input [1000*8-1:0] filename;
+  reg [BITS-1:0] memld [0:WORDS-1];
+  integer i;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
-	$readmemb(filename, memld);
+  $readmemb(filename, memld);
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  for (i=0;i<WORDS;i=i+1) begin
-	  wordtemp = memld[i];
-	  Atemp = i;
-	  mux_address = (Atemp & 1'b1);
+    for (i=0;i<WORDS;i=i+1) begin
+    wordtemp = memld[i];
+    Atemp = i;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -1257,22 +1251,22 @@ task loadmem;
           1'b0, wordtemp[0]} << mux_address);
       row = (row & ~row_mask) | (row_mask & (~row_mask | new_data));
         mem[row_address] = row;
-  	end
+    end
   end
   end
   endtask
 
 task dumpmem;
-	input [1000*8-1:0] filename_dump;
-	integer i, dump_file_desc;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  input [1000*8-1:0] filename_dump;
+  integer i, dump_file_desc;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
-	dump_file_desc = $fopen(filename_dump, "w");
+  dump_file_desc = $fopen(filename_dump, "w");
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  for (i=0;i<WORDS;i=i+1) begin
-	  Atemp = i;
-	  mux_address = (Atemp & 1'b1);
+    for (i=0;i<WORDS;i=i+1) begin
+    Atemp = i;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -1301,24 +1295,24 @@ task dumpmem;
         data_out[32], data_out[30], data_out[28], data_out[26], data_out[24], data_out[22],
         data_out[20], data_out[18], data_out[16], data_out[14], data_out[12], data_out[10],
         data_out[8], data_out[6], data_out[4], data_out[2], data_out[0]};
-        	XQA = 1'b0; QA_update = 1'b1;
-   	$fdisplay(dump_file_desc, "%b", mem_path);
+          XQA = 1'b0; QA_update = 1'b1;
+    $fdisplay(dump_file_desc, "%b", mem_path);
   end
-  	end
+    end
     $fclose(dump_file_desc);
   end
   endtask
 
 task loadaddr;
-	input [4:0] load_addr;
-	input [127:0] load_data;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  input [4:0] load_addr;
+  input [127:0] load_data;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  wordtemp = load_data;
-	  Atemp = load_addr;
-	  mux_address = (Atemp & 1'b1);
+    wordtemp = load_data;
+    Atemp = load_addr;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -1395,14 +1389,14 @@ task loadaddr;
   endtask
 
 task dumpaddr;
-	output [127:0] dump_data;
-	input [4:0] dump_addr;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  output [127:0] dump_data;
+  input [4:0] dump_addr;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  Atemp = dump_addr;
-	  mux_address = (Atemp & 1'b1);
+    Atemp = dump_addr;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -1431,9 +1425,9 @@ task dumpaddr;
         data_out[32], data_out[30], data_out[28], data_out[26], data_out[24], data_out[22],
         data_out[20], data_out[18], data_out[16], data_out[14], data_out[12], data_out[10],
         data_out[8], data_out[6], data_out[4], data_out[2], data_out[0]};
-        	XQA = 1'b0; QA_update = 1'b1;
-   	dump_data = mem_path;
-  	end
+          XQA = 1'b0; QA_update = 1'b1;
+    dump_data = mem_path;
+    end
   end
   endtask
 
@@ -1493,11 +1487,11 @@ task dumpaddr;
         data_out[32], data_out[30], data_out[28], data_out[26], data_out[24], data_out[22],
         data_out[20], data_out[18], data_out[16], data_out[14], data_out[12], data_out[10],
         data_out[8], data_out[6], data_out[4], data_out[2], data_out[0]};
-        	XQA = 1'b0; QA_update = 1'b1;
+          XQA = 1'b0; QA_update = 1'b1;
       end
         if (DFTRAMBYP_int === 1'b1 && SEA_int === 1'b0) begin
         end else if (DFTRAMBYP_int === 1'b1 && SEA_int === 1'bx) begin
-        	XQA = 1'b1; QA_update = 1'b1;
+          XQA = 1'b1; QA_update = 1'b1;
         end
       if( isBitX(DFTRAMBYP_int) ) begin
         XQA = 1'b1; QA_update = 1'b1;
@@ -1647,37 +1641,37 @@ task dumpaddr;
       row = (row & ~row_mask) | (row_mask & (~row_mask | new_data));
         if (DFTRAMBYP_int === 1'b1 && (SEB_int === 1'b0 || SEB_int === 1'bx)) begin
         end else begin
-        	mem[row_address] = row;
+          mem[row_address] = row;
         end
     end
   end
   endtask
   always @ (CENA_ or TCENA_ or TENA_ or DFTRAMBYP_ or CLKA_) begin
-  	if(CLKA_ == 1'b0) begin
-  		CENA_p2 = CENA_;
-  		TCENA_p2 = TCENA_;
-  		DFTRAMBYP_p2 = DFTRAMBYP_;
-  	end
+    if(CLKA_ == 1'b0) begin
+      CENA_p2 = CENA_;
+      TCENA_p2 = TCENA_;
+      DFTRAMBYP_p2 = DFTRAMBYP_;
+    end
   end
 
-// `ifdef POWER_PINS
-//   always @ (VDDCE) begin
-//       if (VDDCE != 1'b1) begin
-//        if (VDDPE == 1'b1) begin
-//         //$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", 0);
-//        end
-//         //$display("In PowerDown Mode in %m at %0t", 0);
-//         failedWrite(0);
-//       end
-//       if (VDDCE == 1'b1) begin
-//        if (VDDPE == 1'b1) begin
-//         //$display("VDDPE should be powered up after VDDCE in %m at %0t", 0);
-//         //$display("Illegal power up sequencing in %m at %0t", 0);
-//        end
-//         failedWrite(0);
-//       end
-//   end
-// `endif
+`ifdef POWER_PINS
+  always @ (VDDCE) begin
+      if (VDDCE != 1'b1) begin
+       if (VDDPE == 1'b1) begin
+        $display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", $time);
+       end
+        $display("In PowerDown Mode in %m at %0t", $time);
+        failedWrite(0);
+      end
+      if (VDDCE == 1'b1) begin
+       if (VDDPE == 1'b1) begin
+        $display("VDDPE should be powered up after VDDCE in %m at %0t", $time);
+        $display("Illegal power up sequencing in %m at %0t", $time);
+       end
+        failedWrite(0);
+      end
+  end
+`endif
 `ifdef POWER_PINS
   always @ (RET1N_ or VDDPE or VDDCE) begin
 `else     
@@ -1754,30 +1748,30 @@ task dumpaddr;
       COLLDISN_int = 1'bx;
     end
     RET1N_int = RET1N_;
-    //#0;
+    #0;
         QA_update = 1'b0;
-    //#0;//#0;  XQA = 1'b0;
+    #0;#0;  XQA = 1'b0;
   end
 
   always @ (CLKB_ or DFTRAMBYP_p2) begin
-  	//#0;
-  	if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
-  	  if (RET1N_ == 1'b1) begin
-	        DB_sh_update = 1'b1; 
-  	  end
-  	end
+    #0;
+    if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
+      if (RET1N_ == 1'b1) begin
+          DB_sh_update = 1'b1; 
+      end
+    end
   end
 
   always @ CLKA_ begin
 // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
-// `ifdef POWER_PINS
-//     if (VDDCE === 1'bx || VDDCE === 1'bz)
-//       //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
-//     if (VDDPE === 1'bx || VDDPE === 1'bz)
-//       //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
-//     if (VSSE === 1'bx || VSSE === 1'bz)
-//       //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
-// `endif
+`ifdef POWER_PINS
+    if (VDDCE === 1'bx || VDDCE === 1'bz)
+      $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
+    if (VDDPE === 1'bx || VDDPE === 1'bz)
+      $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
+    if (VSSE === 1'bx || VSSE === 1'bz)
+      $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
+`endif
 `ifdef POWER_PINS
   if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
 `else     
@@ -1815,7 +1809,7 @@ task dumpaddr;
       end
       clk0_int = 1'b0;
       if (DFTRAMBYP_=== 1'b1 && SEA_ === 1'b1) begin
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
   if (RET1N_ == 1'b1) begin
         XQA = 1'b0; QA_update = 1'b1;
     if (^{(CENA_int & !isBit1(DFTRAMBYP_int)), EMAA_int, EMASA_int, RET1N_int} === 1'bx) 
@@ -1842,12 +1836,12 @@ task dumpaddr;
       end
       clk0_int = 1'b0;
     ReadA;
-      if (CENA_int === 1'b0) previous_CLKA = `REALTIME;
-    //#0;
+      if (CENA_int === 1'b0) previous_CLKA = $realtime;
+    #0;
       if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
          if((|WENB_int) == 1'b1) begin
-          //$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -1877,12 +1871,12 @@ task dumpaddr;
             WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
             WENB_int[2], WENB_int[1], WENB_int[0]};
         mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
-        //#0;
+        #0;
         QA_update = 1'b0;
-        //#0;
+        #0;
         QA_update = 1'b1;
          end else begin
-          //$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -1890,30 +1884,30 @@ task dumpaddr;
          end
       end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           ROW_CC = 1;
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int 
        === 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin
           ROW_CC = 1;
-          //$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
           READ_WRITE = 1;
         DB_int = {128{1'bx}};
         WriteB;
         if (col_contention(AA_int,AB_int)) begin
-          //$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
           COL_CC = 1;
           READ_WRITE = 1;
         XQA = 1'b1; QA_update = 1'b1;
       end else begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end
       end
@@ -2061,11 +2055,11 @@ task dumpaddr;
 
 
   always @ (CENB_ or TCENB_ or TENB_ or DFTRAMBYP_ or CLKB_) begin
-  	if(CLKB_ == 1'b0) begin
-  		CENB_p2 = CENB_;
-  		TCENB_p2 = TCENB_;
-  		DFTRAMBYP_p2 = DFTRAMBYP_;
-  	end
+    if(CLKB_ == 1'b0) begin
+      CENB_p2 = CENB_;
+      TCENB_p2 = TCENB_;
+      DFTRAMBYP_p2 = DFTRAMBYP_;
+    end
   end
 
 `ifdef POWER_PINS
@@ -2150,22 +2144,22 @@ task dumpaddr;
       COLLDISN_int = 1'bx;
     end
     RET1N_int = RET1N_;
-    //#0;
+    #0;
         QA_update = 1'b0;
         DB_sh_update = 1'b0; 
-    //#0;//#0;  XDB_sh = 1'b0; 
+    #0;#0;  XDB_sh = 1'b0; 
   end
 
   always @ CLKB_ begin
 // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
-// `ifdef POWER_PINS
-//     if (VDDCE === 1'bx || VDDCE === 1'bz)
-//       //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
-//     if (VDDPE === 1'bx || VDDPE === 1'bz)
-//       //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
-//     if (VSSE === 1'bx || VSSE === 1'bz)
-//       //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
-// `endif
+`ifdef POWER_PINS
+    if (VDDCE === 1'bx || VDDCE === 1'bz)
+      $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
+    if (VDDPE === 1'bx || VDDPE === 1'bz)
+      $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
+    if (VSSE === 1'bx || VSSE === 1'bz)
+      $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
+`endif
 `ifdef POWER_PINS
   if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
 `else     
@@ -2190,7 +2184,7 @@ task dumpaddr;
       TWENB_int = TWENB_;
       RET1N_int = RET1N_;
       COLLDISN_int = COLLDISN_;
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
       if (DFTRAMBYP_=== 1'b1 || CENB_int != 1'b1) begin
         WENB_int = TENB_ ? WENB_ : TWENB_;
         AB_int = TENB_ ? AB_ : TAB_;
@@ -2203,7 +2197,7 @@ task dumpaddr;
       end
       clk1_int = 1'b0;
       if (DFTRAMBYP_=== 1'b1 && SEB_ === 1'b1) begin
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
     if (^{(CENB_int & !isBit1(DFTRAMBYP_int)), EMAB_int, RET1N_int} === 1'bx) 
       WriteB;
         XDB_sh = 1'b0; 
@@ -2214,7 +2208,7 @@ task dumpaddr;
       TWENB_int = TWENB_;
       RET1N_int = RET1N_;
       COLLDISN_int = COLLDISN_;
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
       if (DFTRAMBYP_=== 1'b1 || CENB_int != 1'b1) begin
         WENB_int = TENB_ ? WENB_ : TWENB_;
         AB_int = TENB_ ? AB_ : TAB_;
@@ -2232,12 +2226,12 @@ task dumpaddr;
       end else begin
       WriteB;
       end
-      if (CENB_int === 1'b0) previous_CLKB = `REALTIME;
-    //#0;
+      if (CENB_int === 1'b0) previous_CLKB = $realtime;
+    #0;
       if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
          if((|WENB_int) == 1'b1) begin
-          //$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -2267,12 +2261,12 @@ task dumpaddr;
             WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
             WENB_int[2], WENB_int[1], WENB_int[0]};
         mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
-        //#0;
+        #0;
         QA_update = 1'b0;
-        //#0;
+        #0;
         QA_update = 1'b1;
          end else begin
-          //$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -2280,30 +2274,30 @@ task dumpaddr;
          end
       end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           ROW_CC = 1;
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int 
        === 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
           ROW_CC = 1;
-          //$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
           READ_WRITE = 1;
         DB_int = {128{1'bx}};
         WriteB;
         if (col_contention(AA_int,AB_int)) begin
-          //$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
           COL_CC = 1;
           READ_WRITE = 1;
         XQA = 1'b1; QA_update = 1'b1;
       end else begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end
       end
@@ -2450,16 +2444,16 @@ task dumpaddr;
 
 
 // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
-// `ifdef POWER_PINS
-//  always @ (VDDCE or VDDPE or VSSE) begin
-//     if (VDDCE === 1'bx || VDDCE === 1'bz)
-//       //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
-//     if (VDDPE === 1'bx || VDDPE === 1'bz)
-//       //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
-//     if (VSSE === 1'bx || VSSE === 1'bz)
-//       //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
-//  end
-// `endif
+`ifdef POWER_PINS
+ always @ (VDDCE or VDDPE or VSSE) begin
+    if (VDDCE === 1'bx || VDDCE === 1'bz)
+      $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
+    if (VDDPE === 1'bx || VDDPE === 1'bz)
+      $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
+    if (VSSE === 1'bx || VSSE === 1'bz)
+      $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
+ end
+`endif
 
   function row_contention;
     input [4:0] aa;
@@ -3618,23 +3612,23 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
 `ifdef INITIALIZE_MEMORY
   integer i;
   initial begin
-    //#0;
+    #0;
     for (i = 0; i < MEM_HEIGHT; i = i + 1)
       mem[i] = {MEM_WIDTH{1'b0}};
   end
 `endif
-  // always @ (EMAA_) begin
-  // 	if(EMAA_ < 3) 
-  //  	//$display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", 0);
-  // end
-  // always @ (EMASA_) begin
-  // 	if(EMASA_ < 0) 
-  //  	//$display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", 0);
-  // end
-  // always @ (EMAB_) begin
-  // 	if(EMAB_ < 3) 
-  //  	//$display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", 0);
-  // end
+  always @ (EMAA_) begin
+    if(EMAA_ < 3) 
+    $display("Warning: Set Value for EMAA doesn't match Default value 3 in %m at %0t", $time);
+  end
+  always @ (EMASA_) begin
+    if(EMASA_ < 0) 
+    $display("Warning: Set Value for EMASA doesn't match Default value 0 in %m at %0t", $time);
+  end
+  always @ (EMAB_) begin
+    if(EMAB_ < 3) 
+    $display("Warning: Set Value for EMAB doesn't match Default value 3 in %m at %0t", $time);
+  end
 
   task failedWrite;
   input port_f;
@@ -3661,18 +3655,18 @@ module rf2_32x128_wm1 (CENYA, AYA, CENYB, WENYB, AYB, QA, SOA, SOB, CLKA, CENA,
 
 
 task loadmem;
-	input [1000*8-1:0] filename;
-	reg [BITS-1:0] memld [0:WORDS-1];
-	integer i;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  input [1000*8-1:0] filename;
+  reg [BITS-1:0] memld [0:WORDS-1];
+  integer i;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
-	$readmemb(filename, memld);
+  $readmemb(filename, memld);
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  for (i=0;i<WORDS;i=i+1) begin
-	  wordtemp = memld[i];
-	  Atemp = i;
-	  mux_address = (Atemp & 1'b1);
+    for (i=0;i<WORDS;i=i+1) begin
+    wordtemp = memld[i];
+    Atemp = i;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -3744,22 +3738,22 @@ task loadmem;
           1'b0, wordtemp[0]} << mux_address);
       row = (row & ~row_mask) | (row_mask & (~row_mask | new_data));
         mem[row_address] = row;
-  	end
+    end
   end
   end
   endtask
 
 task dumpmem;
-	input [1000*8-1:0] filename_dump;
-	integer i, dump_file_desc;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  input [1000*8-1:0] filename_dump;
+  integer i, dump_file_desc;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
-	dump_file_desc = $fopen(filename_dump, "w");
+  dump_file_desc = $fopen(filename_dump, "w");
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  for (i=0;i<WORDS;i=i+1) begin
-	  Atemp = i;
-	  mux_address = (Atemp & 1'b1);
+    for (i=0;i<WORDS;i=i+1) begin
+    Atemp = i;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -3788,24 +3782,24 @@ task dumpmem;
         data_out[32], data_out[30], data_out[28], data_out[26], data_out[24], data_out[22],
         data_out[20], data_out[18], data_out[16], data_out[14], data_out[12], data_out[10],
         data_out[8], data_out[6], data_out[4], data_out[2], data_out[0]};
-        	XQA = 1'b0; QA_update = 1'b1;
-   	$fdisplay(dump_file_desc, "%b", mem_path);
+          XQA = 1'b0; QA_update = 1'b1;
+    $fdisplay(dump_file_desc, "%b", mem_path);
   end
-  	end
+    end
     $fclose(dump_file_desc);
   end
   endtask
 
 task loadaddr;
-	input [4:0] load_addr;
-	input [127:0] load_data;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  input [4:0] load_addr;
+  input [127:0] load_data;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  wordtemp = load_data;
-	  Atemp = load_addr;
-	  mux_address = (Atemp & 1'b1);
+    wordtemp = load_data;
+    Atemp = load_addr;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -3882,14 +3876,14 @@ task loadaddr;
   endtask
 
 task dumpaddr;
-	output [127:0] dump_data;
-	input [4:0] dump_addr;
-	reg [BITS-1:0] wordtemp;
-	reg [4:0] Atemp;
+  output [127:0] dump_data;
+  input [4:0] dump_addr;
+  reg [BITS-1:0] wordtemp;
+  reg [4:0] Atemp;
   begin
      if (CENA_ === 1'b1 && CENB_ === 1'b1) begin
-	  Atemp = dump_addr;
-	  mux_address = (Atemp & 1'b1);
+    Atemp = dump_addr;
+    mux_address = (Atemp & 1'b1);
       row_address = (Atemp >> 1);
       row = mem[row_address];
         writeEnable = {128{1'b1}};
@@ -3918,9 +3912,9 @@ task dumpaddr;
         data_out[32], data_out[30], data_out[28], data_out[26], data_out[24], data_out[22],
         data_out[20], data_out[18], data_out[16], data_out[14], data_out[12], data_out[10],
         data_out[8], data_out[6], data_out[4], data_out[2], data_out[0]};
-        	XQA = 1'b0; QA_update = 1'b1;
-   	dump_data = mem_path;
-  	end
+          XQA = 1'b0; QA_update = 1'b1;
+    dump_data = mem_path;
+    end
   end
   endtask
 
@@ -3980,11 +3974,11 @@ task dumpaddr;
         data_out[32], data_out[30], data_out[28], data_out[26], data_out[24], data_out[22],
         data_out[20], data_out[18], data_out[16], data_out[14], data_out[12], data_out[10],
         data_out[8], data_out[6], data_out[4], data_out[2], data_out[0]};
-        	XQA = 1'b0; QA_update = 1'b1;
+          XQA = 1'b0; QA_update = 1'b1;
       end
         if (DFTRAMBYP_int === 1'b1 && SEA_int === 1'b0) begin
         end else if (DFTRAMBYP_int === 1'b1 && SEA_int === 1'bx) begin
-        	XQA = 1'b1; QA_update = 1'b1;
+          XQA = 1'b1; QA_update = 1'b1;
         end
       if( isBitX(DFTRAMBYP_int) ) begin
         XQA = 1'b1; QA_update = 1'b1;
@@ -4134,37 +4128,37 @@ task dumpaddr;
       row = (row & ~row_mask) | (row_mask & (~row_mask | new_data));
         if (DFTRAMBYP_int === 1'b1 && (SEB_int === 1'b0 || SEB_int === 1'bx)) begin
         end else begin
-        	mem[row_address] = row;
+          mem[row_address] = row;
         end
     end
   end
   endtask
   always @ (CENA_ or TCENA_ or TENA_ or DFTRAMBYP_ or CLKA_) begin
-  	if(CLKA_ == 1'b0) begin
-  		CENA_p2 = CENA_;
-  		TCENA_p2 = TCENA_;
-  		DFTRAMBYP_p2 = DFTRAMBYP_;
-  	end
+    if(CLKA_ == 1'b0) begin
+      CENA_p2 = CENA_;
+      TCENA_p2 = TCENA_;
+      DFTRAMBYP_p2 = DFTRAMBYP_;
+    end
   end
 
-// `ifdef POWER_PINS
-//   always @ (VDDCE) begin
-//       if (VDDCE != 1'b1) begin
-//        if (VDDPE == 1'b1) begin
-//         //$display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", 0);
-//        end
-//         //$display("In PowerDown Mode in %m at %0t", 0);
-//         failedWrite(0);
-//       end
-//       if (VDDCE == 1'b1) begin
-//        if (VDDPE == 1'b1) begin
-//         //$display("VDDPE should be powered up after VDDCE in %m at %0t", 0);
-//         //$display("Illegal power up sequencing in %m at %0t", 0);
-//        end
-//         failedWrite(0);
-//       end
-//   end
-// `endif
+`ifdef POWER_PINS
+  always @ (VDDCE) begin
+      if (VDDCE != 1'b1) begin
+       if (VDDPE == 1'b1) begin
+        $display("VDDCE should be powered down after VDDPE, Illegal power down sequencing in %m at %0t", $time);
+       end
+        $display("In PowerDown Mode in %m at %0t", $time);
+        failedWrite(0);
+      end
+      if (VDDCE == 1'b1) begin
+       if (VDDPE == 1'b1) begin
+        $display("VDDPE should be powered up after VDDCE in %m at %0t", $time);
+        $display("Illegal power up sequencing in %m at %0t", $time);
+       end
+        failedWrite(0);
+      end
+  end
+`endif
 `ifdef POWER_PINS
   always @ (RET1N_ or VDDPE or VDDCE) begin
 `else     
@@ -4241,30 +4235,30 @@ task dumpaddr;
       COLLDISN_int = 1'bx;
     end
     RET1N_int = RET1N_;
-    //#0;
+    #0;
         QA_update = 1'b0;
-    //#0;//#0;  XQA = 1'b0;
+    #0;#0;  XQA = 1'b0;
   end
 
   always @ (CLKB_ or DFTRAMBYP_p2) begin
-  	//#0;
-  	if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
-  	  if (RET1N_ == 1'b1) begin
-	        DB_sh_update = 1'b1; 
-  	  end
-  	end
+    #0;
+    if(CLKB_ == 1'b1 && (DFTRAMBYP_int === 1'b1 || CENB_int != 1'b1)) begin
+      if (RET1N_ == 1'b1) begin
+          DB_sh_update = 1'b1; 
+      end
+    end
   end
 
   always @ CLKA_ begin
 // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
-// `ifdef POWER_PINS
-//     if (VDDCE === 1'bx || VDDCE === 1'bz)
-//       //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
-//     if (VDDPE === 1'bx || VDDPE === 1'bz)
-//       //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
-//     if (VSSE === 1'bx || VSSE === 1'bz)
-//       //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
-// `endif
+`ifdef POWER_PINS
+    if (VDDCE === 1'bx || VDDCE === 1'bz)
+      $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
+    if (VDDPE === 1'bx || VDDPE === 1'bz)
+      $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
+    if (VSSE === 1'bx || VSSE === 1'bz)
+      $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
+`endif
 `ifdef POWER_PINS
   if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
 `else     
@@ -4302,7 +4296,7 @@ task dumpaddr;
       end
       clk0_int = 1'b0;
       if (DFTRAMBYP_=== 1'b1 && SEA_ === 1'b1) begin
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
   if (RET1N_ == 1'b1) begin
         XQA = 1'b0; QA_update = 1'b1;
     if (^{(CENA_int & !isBit1(DFTRAMBYP_int)), EMAA_int, EMASA_int, RET1N_int} === 1'bx) 
@@ -4329,12 +4323,12 @@ task dumpaddr;
       end
       clk0_int = 1'b0;
     ReadA;
-      if (CENA_int === 1'b0) previous_CLKA = `REALTIME;
-    //#0;
+      if (CENA_int === 1'b0) previous_CLKA = $realtime;
+    #0;
       if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && is_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
          if((|WENB_int) == 1'b1) begin
-          //$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4364,12 +4358,12 @@ task dumpaddr;
             WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
             WENB_int[2], WENB_int[1], WENB_int[0]};
         mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
-        //#0;
+        #0;
         QA_update = 1'b0;
-        //#0;
+        #0;
         QA_update = 1'b1;
          end else begin
-          //$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4377,30 +4371,30 @@ task dumpaddr;
          end
       end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && COLLDISN_int === 1'b1 && row_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           ROW_CC = 1;
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int 
        === 1'bx) && row_contention(AA_int, AB_int, 1'b1, 1'b0)) begin
           ROW_CC = 1;
-          //$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
           READ_WRITE = 1;
         DB_int = {128{1'bx}};
         WriteB;
         if (col_contention(AA_int,AB_int)) begin
-          //$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
           COL_CC = 1;
           READ_WRITE = 1;
         XQA = 1'b1; QA_update = 1'b1;
       end else begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end
       end
@@ -4419,7 +4413,7 @@ task dumpaddr;
   initial cont_flag0_int = 1'b0;
 
   always @ globalNotifier0 begin
-    if (`REALTIME == 0) begin
+    if ($realtime == 0) begin
     end else if ((EMAA_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAA_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) || 
       (EMAA_int[2] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMASA_int === 1'bx & DFTRAMBYP_int === 1'b1)
       ) begin
@@ -4442,7 +4436,7 @@ task dumpaddr;
       AB_int, 1'b1, 1'b0)) begin
       cont_flag0_int = 1'b0;
          if((|WENB_int) == 1'b1) begin
-          //$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4471,12 +4465,12 @@ task dumpaddr;
             WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
             WENB_int[2], WENB_int[1], WENB_int[0]};
         mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
-        //#0;
+        #0;
         QA_update = 1'b0;
-        //#0;
+        #0;
         QA_update = 1'b1;
          end else begin
-          //$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4486,26 +4480,26 @@ task dumpaddr;
      1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
       cont_flag0_int = 1'b0;
           ROW_CC = 1;
-          //$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
           READ_WRITE = 1;
         DB_int = {128{1'bx}};
         WriteB;
         if (col_contention(AA_int,AB_int)) begin
-          //$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
           COL_CC = 1;
           READ_WRITE = 1;
         XQA = 1'b1; QA_update = 1'b1;
       end else begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end
     end else begin
-      //#0;//#0;
+      #0;#0;
       ReadA;
    end
-      //#0;
+      #0;
         QA_update = 1'b0;
     globalNotifier0 = 1'b0;
   end
@@ -4644,11 +4638,11 @@ task dumpaddr;
 
 
   always @ (CENB_ or TCENB_ or TENB_ or DFTRAMBYP_ or CLKB_) begin
-  	if(CLKB_ == 1'b0) begin
-  		CENB_p2 = CENB_;
-  		TCENB_p2 = TCENB_;
-  		DFTRAMBYP_p2 = DFTRAMBYP_;
-  	end
+    if(CLKB_ == 1'b0) begin
+      CENB_p2 = CENB_;
+      TCENB_p2 = TCENB_;
+      DFTRAMBYP_p2 = DFTRAMBYP_;
+    end
   end
 
 `ifdef POWER_PINS
@@ -4733,22 +4727,22 @@ task dumpaddr;
       COLLDISN_int = 1'bx;
     end
     RET1N_int = RET1N_;
-    //#0;
+    #0;
         QA_update = 1'b0;
         DB_sh_update = 1'b0; 
-    //#0;//#0;  XDB_sh = 1'b0; 
+    #0;#0;  XDB_sh = 1'b0; 
   end
 
   always @ CLKB_ begin
 // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
-// `ifdef POWER_PINS
-//     if (VDDCE === 1'bx || VDDCE === 1'bz)
-//       //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
-//     if (VDDPE === 1'bx || VDDPE === 1'bz)
-//       //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
-//     if (VSSE === 1'bx || VSSE === 1'bz)
-//       //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
-// `endif
+`ifdef POWER_PINS
+    if (VDDCE === 1'bx || VDDCE === 1'bz)
+      $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
+    if (VDDPE === 1'bx || VDDPE === 1'bz)
+      $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
+    if (VSSE === 1'bx || VSSE === 1'bz)
+      $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
+`endif
 `ifdef POWER_PINS
   if (RET1N_ == 1'b0 && VDDPE == 1'b0) begin
 `else     
@@ -4773,7 +4767,7 @@ task dumpaddr;
       TWENB_int = TWENB_;
       RET1N_int = RET1N_;
       COLLDISN_int = COLLDISN_;
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
       if (DFTRAMBYP_=== 1'b1 || CENB_int != 1'b1) begin
         WENB_int = TENB_ ? WENB_ : TWENB_;
         AB_int = TENB_ ? AB_ : TAB_;
@@ -4786,7 +4780,7 @@ task dumpaddr;
       end
       clk1_int = 1'b0;
       if (DFTRAMBYP_=== 1'b1 && SEB_ === 1'b1) begin
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
     if (^{(CENB_int & !isBit1(DFTRAMBYP_int)), EMAB_int, RET1N_int} === 1'bx) 
       WriteB;
         XDB_sh = 1'b0; 
@@ -4797,7 +4791,7 @@ task dumpaddr;
       TWENB_int = TWENB_;
       RET1N_int = RET1N_;
       COLLDISN_int = COLLDISN_;
-      	DFTRAMBYP_int = DFTRAMBYP_;
+        DFTRAMBYP_int = DFTRAMBYP_;
       if (DFTRAMBYP_=== 1'b1 || CENB_int != 1'b1) begin
         WENB_int = TENB_ ? WENB_ : TWENB_;
         AB_int = TENB_ ? AB_ : TAB_;
@@ -4815,12 +4809,12 @@ task dumpaddr;
       end else begin
       WriteB;
       end
-      if (CENB_int === 1'b0) previous_CLKB = `REALTIME;
-    //#0;
+      if (CENB_int === 1'b0) previous_CLKB = $realtime;
+    #0;
       if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && is_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
          if((|WENB_int) == 1'b1) begin
-          //$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4850,12 +4844,12 @@ task dumpaddr;
             WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
             WENB_int[2], WENB_int[1], WENB_int[0]};
         mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
-        //#0;
+        #0;
         QA_update = 1'b0;
-        //#0;
+        #0;
         QA_update = 1'b1;
          end else begin
-          //$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4863,30 +4857,30 @@ task dumpaddr;
          end
       end else if (((previous_CLKA == previous_CLKB)) && COLLDISN_int === 1'b1 && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && row_contention(AA_int,
         AB_int, 1'b1, 1'b0)) begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s row contention: in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s row contention: in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           ROW_CC = 1;
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: write B succeeds, read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end else if (((previous_CLKA == previous_CLKB)) && (CENA_int !== 1'b1 && CENB_int !== 1'b1 && DFTRAMBYP_ !== 1'b1) && (COLLDISN_int === 1'b0 || COLLDISN_int 
        === 1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
           ROW_CC = 1;
-          //$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
           READ_WRITE = 1;
         DB_int = {128{1'bx}};
         WriteB;
         if (col_contention(AA_int,AB_int)) begin
-          //$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
           COL_CC = 1;
           READ_WRITE = 1;
         XQA = 1'b1; QA_update = 1'b1;
       end else begin
-// `ifdef ARM_MESSAGES
-//           //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
-// `endif
+`ifdef ARM_MESSAGES
+          $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
+`endif
           READ_WRITE = 1;
       end
       end
@@ -4904,7 +4898,7 @@ task dumpaddr;
   initial cont_flag1_int = 1'b0;
 
   always @ globalNotifier1 begin
-    if (`REALTIME == 0) begin
+    if ($realtime == 0) begin
     end else if ((EMAB_int[0] === 1'bx & DFTRAMBYP_int === 1'b1) || (EMAB_int[1] === 1'bx & DFTRAMBYP_int === 1'b1) || 
       (EMAB_int[2] === 1'bx & DFTRAMBYP_int === 1'b1)) begin
         XDB_sh = 1'b1; 
@@ -4930,7 +4924,7 @@ task dumpaddr;
       AB_int, 1'b1, 1'b0)) begin
       cont_flag1_int = 1'b0;
          if((|WENB_int) == 1'b1) begin
-          //$display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B partially, read A partially in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4959,12 +4953,12 @@ task dumpaddr;
             WENB_int[8], WENB_int[7], WENB_int[6], WENB_int[5], WENB_int[4], WENB_int[3],
             WENB_int[2], WENB_int[1], WENB_int[0]};
         mem_path = (partial_mask & {128{1'bx}}) | (~partial_mask & mem_path);
-        //#0;
+        #0;
         QA_update = 1'b0;
-        //#0;
+        #0;
         QA_update = 1'b1;
          end else begin
-          //$display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B succeeds, read A fails in %m at %0t",ASSERT_PREFIX, $time);
           ROW_CC = 1;
           COL_CC = 1;
           READ_WRITE = 1;
@@ -4974,26 +4968,26 @@ task dumpaddr;
      1'bx) && row_contention(AA_int, AB_int,1'b1, 1'b0)) begin
       cont_flag1_int = 1'b0;
           ROW_CC = 1;
-          //$display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: write B fails in %m at %0t",ASSERT_PREFIX, $time);
           READ_WRITE = 1;
         DB_int = {128{1'bx}};
         WriteB;
         if (col_contention(AA_int,AB_int)) begin
-          //$display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: read A fails in %m at %0t",ASSERT_PREFIX, $time);
           COL_CC = 1;
           READ_WRITE = 1;
         XQA = 1'b1; QA_update = 1'b1;
       end else begin
 `ifdef ARM_MESSAGES
-          //$display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, 0);
+          $display("%s contention: read A succeeds in %m at %0t",ASSERT_PREFIX, $time);
 `endif
           READ_WRITE = 1;
       end
     end else begin
-      //#0;//#0;
+      #0;#0;
       WriteB;
    end
-      //#0;
+      #0;
         DB_sh_update = 1'b0; 
     globalNotifier1 = 1'b0;
   end
@@ -5132,16 +5126,16 @@ task dumpaddr;
 
 
 // If POWER_PINS is defined at Simulator Command Line, it selects the module definition with Power Ports
-// `ifdef POWER_PINS
-//  always @ (VDDCE or VDDPE or VSSE) begin
-//     if (VDDCE === 1'bx || VDDCE === 1'bz)
-//       //$display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, 0);
-//     if (VDDPE === 1'bx || VDDPE === 1'bz)
-//       //$display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, 0);
-//     if (VSSE === 1'bx || VSSE === 1'bz)
-//       //$display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, 0);
-//  end
-// `endif
+`ifdef POWER_PINS
+ always @ (VDDCE or VDDPE or VSSE) begin
+    if (VDDCE === 1'bx || VDDCE === 1'bz)
+      $display("Warning: Unknown value for VDDCE %b in %m at %0t", VDDCE, $time);
+    if (VDDPE === 1'bx || VDDPE === 1'bz)
+      $display("Warning: Unknown value for VDDPE %b in %m at %0t", VDDPE, $time);
+    if (VSSE === 1'bx || VSSE === 1'bz)
+      $display("Warning: Unknown value for VSSE %b in %m at %0t", VSSE, $time);
+ end
+`endif
 
   function row_contention;
     input [4:0] aa;
@@ -15364,9 +15358,4 @@ begin
    else
       Q_out = Q_in;
    end
-endmodule
-
-
-/* verilator lint_on UNUSED */
-
-
+endmodule
\ No newline at end of file
diff --git a/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp b/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp
new file mode 100644
index 00000000..ac1ac49d
--- /dev/null
+++ b/models/memory/cln28hpc/rf2_32x128_wm1/testbench.cpp
@@ -0,0 +1,19 @@
+
+
+#include "Vrf2_32x128_wm1_rtl.h"
+#include "verilated.h"
+
+int main()
+{
+	Vrf2_32x128_wm1_rtl module;
+
+	for (int i = 0; i < 10; i++)
+	{
+		// module.clk = 0;
+    	module.eval();
+        // module.clk = 1;
+        module.eval();
+	}
+
+	return 0;
+}
\ No newline at end of file