From 0a88c97485477dcd855893eb763e7b0e865ab2fa Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Sun, 29 Mar 2020 16:06:13 -0700 Subject: [PATCH] Another reset issue... --- rtl/VX_cache/VX_cache_miss_resrv.v | 3 +++ rtl/VX_cache/VX_cache_req_queue.v | 1 + 2 files changed, 4 insertions(+) diff --git a/rtl/VX_cache/VX_cache_miss_resrv.v b/rtl/VX_cache/VX_cache_miss_resrv.v index 3bf48c59..3efae933 100644 --- a/rtl/VX_cache/VX_cache_miss_resrv.v +++ b/rtl/VX_cache/VX_cache_miss_resrv.v @@ -132,6 +132,9 @@ module VX_cache_miss_resrv ready_table <= 0; addr_table <= 0; pc_table <= 0; + size <= 0; + head_ptr <= 0; + tail_ptr <= 0; end else begin if (mrvq_push) begin valid_table[enqueue_index] <= 1; diff --git a/rtl/VX_cache/VX_cache_req_queue.v b/rtl/VX_cache/VX_cache_req_queue.v index e4b20e80..2bd111d4 100644 --- a/rtl/VX_cache/VX_cache_req_queue.v +++ b/rtl/VX_cache/VX_cache_req_queue.v @@ -175,6 +175,7 @@ module VX_cache_req_queue always @(posedge clk) begin if (reset) begin + updated_valids <= 0; use_per_valids <= 0; use_per_addr <= 0; use_per_writedata <= 0;