diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index f5034091..103bc6e6 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -16,7 +16,7 @@ `endif `ifndef NUM_THREADS -`define NUM_THREADS 8 +`define NUM_THREADS 4 `endif `ifndef NUM_BARRIERS @@ -36,7 +36,7 @@ `endif `ifndef L1_BLOCK_SIZE -`define L1_BLOCK_SIZE 16 +`define L1_BLOCK_SIZE (`NUM_THREADS * 4) `endif `ifndef STARTUP_ADDR diff --git a/hw/rtl/VX_io_arb.v b/hw/rtl/VX_io_arb.v index 227194a7..54b09ea5 100644 --- a/hw/rtl/VX_io_arb.v +++ b/hw/rtl/VX_io_arb.v @@ -43,40 +43,40 @@ module VX_io_arb #( input wire [WORD_WIDTH-1:0] io_rsp_data_out, output wire io_rsp_ready_out ); - wire [NUM_REQS-1:0] valids; - for (genvar i = 0; i < NUM_REQS; i++) begin - assign valids[i] = (| io_req_valid_in[i]); - end - - wire [NUM_REQS-1:0][(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH))-1:0] data_in; - for (genvar i = 0; i < NUM_REQS; i++) begin - assign data_in[i] = {{io_req_valid_in[i], io_req_tag_in[i], REQS_BITS'(i)}, io_req_addr_in[i], io_req_rw_in[i], io_req_byteen_in[i], io_req_data_in[i]}; - end - - wire [`NUM_THREADS-1:0] io_req_tmask_out; - wire io_req_valid_out_unqual; - - VX_stream_arbiter #( - .NUM_REQS(NUM_REQS), - .DATAW(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH)), - .BUFFERED(NUM_REQS >= 4) - ) req_arb ( - .clk (clk), - .reset (reset), - .valid_in (valids), - .valid_out (io_req_valid_out_unqual), - .data_in (data_in), - .data_out ({io_req_tmask_out, io_req_tag_out, io_req_addr_out, io_req_rw_out, io_req_byteen_out, io_req_data_out}), - .ready_in (io_req_ready_in), - .ready_out (io_req_ready_out) - ); - - assign io_req_valid_out = {`NUM_THREADS{io_req_valid_out_unqual}} & io_req_tmask_out; - - /////////////////////////////////////////////////////////////////////// - if (NUM_REQS > 1) begin + wire [NUM_REQS-1:0] valids; + for (genvar i = 0; i < NUM_REQS; i++) begin + assign valids[i] = (| io_req_valid_in[i]); + end + + wire [NUM_REQS-1:0][(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH))-1:0] data_in; + for (genvar i = 0; i < NUM_REQS; i++) begin + assign data_in[i] = {io_req_valid_in[i], {io_req_tag_in[i], REQS_BITS'(i)}, io_req_addr_in[i], io_req_rw_in[i], io_req_byteen_in[i], io_req_data_in[i]}; + end + + wire [`NUM_THREADS-1:0] io_req_tmask_out; + wire io_req_valid_out_unqual; + + VX_stream_arbiter #( + .NUM_REQS(NUM_REQS), + .DATAW(`NUM_THREADS + TAG_OUT_WIDTH + (`NUM_THREADS * ADDR_WIDTH) + 1 + (`NUM_THREADS * WORD_SIZE) + (`NUM_THREADS * WORD_WIDTH)), + .BUFFERED(NUM_REQS >= 4) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (valids), + .valid_out (io_req_valid_out_unqual), + .data_in (data_in), + .data_out ({io_req_tmask_out, io_req_tag_out, io_req_addr_out, io_req_rw_out, io_req_byteen_out, io_req_data_out}), + .ready_in (io_req_ready_in), + .ready_out (io_req_ready_out) + ); + + assign io_req_valid_out = {`NUM_THREADS{io_req_valid_out_unqual}} & io_req_tmask_out; + + /////////////////////////////////////////////////////////////////////// + wire [REQS_BITS-1:0] rsp_sel = io_rsp_tag_out[REQS_BITS-1:0]; for (genvar i = 0; i < NUM_REQS; i++) begin @@ -92,6 +92,14 @@ module VX_io_arb #( `UNUSED_VAR (clk) `UNUSED_VAR (reset) + assign io_req_valid_out = io_req_valid_in; + assign io_req_tag_out = io_req_tag_in; + assign io_req_addr_out = io_req_addr_in; + assign io_req_rw_out = io_req_rw_in; + assign io_req_byteen_out = io_req_byteen_in; + assign io_req_data_out = io_req_data_in; + assign io_req_ready_in = io_req_ready_out; + assign io_rsp_valid_in = io_rsp_valid_out; assign io_rsp_tag_in = io_rsp_tag_out; assign io_rsp_data_in = io_rsp_data_out; diff --git a/hw/rtl/VX_mem_arb.v b/hw/rtl/VX_mem_arb.v index e8e39b70..1e0997c1 100644 --- a/hw/rtl/VX_mem_arb.v +++ b/hw/rtl/VX_mem_arb.v @@ -43,30 +43,30 @@ module VX_mem_arb #( input wire [DATA_WIDTH-1:0] rsp_data_in, output wire rsp_ready_in ); - wire [NUM_REQS-1:0][(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH)-1:0] data_in; - for (genvar i = 0; i < NUM_REQS; i++) begin - assign data_in[i] = {{req_tag_in[i], REQS_BITS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]}; - end - - VX_stream_arbiter #( - .NUM_REQS(NUM_REQS), - .DATAW(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH), - .BUFFERED(NUM_REQS >= 4) - ) req_arb ( - .clk (clk), - .reset (reset), - .valid_in (req_valid_in), - .valid_out (req_valid_out), - .data_in (data_in), - .data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}), - .ready_in (req_ready_in), - .ready_out (req_ready_out) - ); - - /////////////////////////////////////////////////////////////////////// - if (NUM_REQS > 1) begin + wire [NUM_REQS-1:0][(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH)-1:0] data_in; + for (genvar i = 0; i < NUM_REQS; i++) begin + assign data_in[i] = {{req_tag_in[i], REQS_BITS'(i)}, req_addr_in[i], req_rw_in[i], req_byteen_in[i], req_data_in[i]}; + end + + VX_stream_arbiter #( + .NUM_REQS(NUM_REQS), + .DATAW(TAG_OUT_WIDTH + ADDR_WIDTH + 1 + DATA_SIZE + DATA_WIDTH), + .BUFFERED(NUM_REQS >= 4) + ) req_arb ( + .clk (clk), + .reset (reset), + .valid_in (req_valid_in), + .valid_out (req_valid_out), + .data_in (data_in), + .data_out ({req_tag_out, req_addr_out, req_rw_out, req_byteen_out, req_data_out}), + .ready_in (req_ready_in), + .ready_out (req_ready_out) + ); + + /////////////////////////////////////////////////////////////////////// + wire [REQS_BITS-1:0] rsp_sel = rsp_tag_in [REQS_BITS-1:0]; for (genvar i = 0; i < NUM_REQS; i++) begin diff --git a/hw/rtl/cache/VX_cache.v b/hw/rtl/cache/VX_cache.v index b29416f0..1d3910b0 100644 --- a/hw/rtl/cache/VX_cache.v +++ b/hw/rtl/cache/VX_cache.v @@ -6,13 +6,13 @@ module VX_cache #( // Size of cache in bytes parameter CACHE_SIZE = 8092, // Size of line inside a bank in bytes - parameter BANK_LINE_SIZE = 64, + parameter BANK_LINE_SIZE = 16, // Number of banks parameter NUM_BANKS = 4, // Size of a word in bytes parameter WORD_SIZE = 4, // Number of Word requests per cycle - parameter NUM_REQS = 4, + parameter NUM_REQS = NUM_BANKS, // Core Request Queue Size parameter CREQ_SIZE = 4, @@ -39,14 +39,14 @@ module VX_cache #( // Enable cache flush parameter FLUSH_ENABLE = 1, - // core request tag size - parameter CORE_TAG_WIDTH = 4, - // size of tag id in core request tag - parameter CORE_TAG_ID_BITS = 0, + parameter CORE_TAG_ID_BITS = $clog2(MSHR_SIZE), + + // core request tag size + parameter CORE_TAG_WIDTH = CORE_TAG_ID_BITS, // dram request tag size - parameter DRAM_TAG_WIDTH = 28, + parameter DRAM_TAG_WIDTH = (32 - $clog2(BANK_LINE_SIZE)), // Snooping request tag width parameter SNP_TAG_WIDTH = 1 diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index f7e54431..6fd0fc9a 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -62,6 +62,7 @@ module VX_cache_core_rsp_merge #( end end end + end else begin always @(*) begin @@ -80,6 +81,7 @@ module VX_cache_core_rsp_merge #( end end end + end wire stall = ~core_rsp_ready && (| core_rsp_valid); @@ -100,30 +102,51 @@ module VX_cache_core_rsp_merge #( for (genvar i = 0; i < NUM_BANKS; i++) begin assign per_bank_core_rsp_ready[i] = core_rsp_bank_select[i] && ~stall; end + end else begin + `UNUSED_VAR (clk) `UNUSED_VAR (reset) if (NUM_REQS > 1) begin - assign core_rsp_valid[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_valid; + reg [NUM_REQS-1:0] core_rsp_valid_unqual; + reg [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag_unqual; + reg [NUM_REQS-1:0][`WORD_WIDTH-1:0] core_rsp_data_unqual; + if (CORE_TAG_ID_BITS != 0) begin - assign core_rsp_tag = per_bank_core_rsp_tag[0]; + always @(*) begin + core_rsp_valid_unqual = 0; + core_rsp_tag_unqual = per_bank_core_rsp_tag[0]; + core_rsp_data_unqual = 'x; + core_rsp_valid_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_valid; + core_rsp_data_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_data[0]; + end end else begin - assign core_rsp_tag[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_tag[0]; + always @(*) begin + core_rsp_valid_unqual = 0; + core_rsp_tag_unqual = 'x; + core_rsp_data_unqual = 'x; + core_rsp_valid_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_valid; + core_rsp_tag_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_tag[0]; + core_rsp_data_unqual[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_data[0]; + end end - assign core_rsp_data[per_bank_core_rsp_tid[0]] = per_bank_core_rsp_data[0]; + + assign core_rsp_valid = core_rsp_valid_unqual; + assign core_rsp_tag = core_rsp_tag_unqual; + assign core_rsp_data = core_rsp_data_unqual; assign per_bank_core_rsp_ready[0] = core_rsp_ready; end else begin `UNUSED_VAR(per_bank_core_rsp_tid) assign core_rsp_valid = per_bank_core_rsp_valid; - assign core_rsp_tag = per_bank_core_rsp_tag[0]; - assign core_rsp_data = per_bank_core_rsp_data[0]; + assign core_rsp_tag = per_bank_core_rsp_tag[0]; + assign core_rsp_data = per_bank_core_rsp_data[0]; assign per_bank_core_rsp_ready[0] = core_rsp_ready; - end + end end endmodule