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floating-point CSR fix

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This commit is contained in:
Blaise Tine
2021-03-01 01:46:41 -08:00
parent b441870789
commit 0e3872ee94
1 changed files with 16 additions and 25 deletions
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39
hw/rtl/VX_csr_data.v
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@@ -38,35 +38,26 @@ module VX_csr_data #(
reg [63:0] csr_cycle; reg [63:0] csr_cycle;
reg [63:0] csr_instret; reg [63:0] csr_instret;
reg [`FFG_BITS-1:0] csr_fflags [`NUM_WARPS-1:0]; reg [`NUM_WARPS-1:0][`FRM_BITS+`FFG_BITS-1:0] fcsr;
reg [`FRM_BITS-1:0] csr_frm [`NUM_WARPS-1:0];
reg [`FRM_BITS+`FFG_BITS-1:0] csr_fcsr [`NUM_WARPS-1:0]; // fflags + frm
reg [31:0] read_data_r; reg [31:0] read_data_r;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin
fcsr <= '0;
end
if (fpu_to_csr_if.write_enable) begin if (fpu_to_csr_if.write_enable) begin
csr_fflags[fpu_to_csr_if.write_wid] <= fpu_to_csr_if.write_fflags; fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] <= fpu_to_csr_if.write_fflags
csr_fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0] <= fpu_to_csr_if.write_fflags; | fcsr[fpu_to_csr_if.write_wid][`FFG_BITS-1:0];
end end
if (write_enable) begin if (write_enable) begin
case (write_addr) case (write_addr)
`CSR_FFLAGS: begin `CSR_FFLAGS: fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0];
csr_fcsr[write_wid][`FFG_BITS-1:0] <= write_data[`FFG_BITS-1:0]; `CSR_FRM: fcsr[write_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0]; `CSR_FCSR: fcsr[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0];
end
`CSR_FRM: begin
csr_fcsr[write_wid][`FFG_BITS+`FRM_BITS-1:`FFG_BITS] <= write_data[`FRM_BITS-1:0];
csr_frm[write_wid] <= write_data[`FRM_BITS-1:0];
end
`CSR_FCSR: begin
csr_fcsr[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:0];
csr_frm[write_wid] <= write_data[`FFG_BITS+`FRM_BITS-1:`FFG_BITS];
csr_fflags[write_wid] <= write_data[`FFG_BITS-1:0];
end
`CSR_SATP: csr_satp <= write_data; `CSR_SATP: csr_satp <= write_data;
@@ -105,9 +96,9 @@ module VX_csr_data #(
always @(*) begin always @(*) begin
read_data_r = 'x; read_data_r = 'x;
case (read_addr) case (read_addr)
`CSR_FFLAGS : read_data_r = 32'(csr_fflags[read_wid]); `CSR_FFLAGS : read_data_r = 32'(fcsr[read_wid][`FFG_BITS-1:0]);
`CSR_FRM : read_data_r = 32'(csr_frm[read_wid]); `CSR_FRM : read_data_r = 32'(fcsr[read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS]);
`CSR_FCSR : read_data_r = 32'(csr_fcsr[read_wid]); `CSR_FCSR : read_data_r = 32'(fcsr[read_wid]);
`CSR_WTID , `CSR_WTID ,
`CSR_LTID , `CSR_LTID ,
@@ -210,6 +201,6 @@ module VX_csr_data #(
end end
assign read_data = read_data_r; assign read_data = read_data_r;
assign fpu_to_csr_if.read_frm = csr_frm[fpu_to_csr_if.read_wid]; assign fpu_to_csr_if.read_frm = fcsr[fpu_to_csr_if.read_wid][`FRM_BITS+`FFG_BITS-1:`FFG_BITS];
endmodule endmodule