From 106d7070243c7c3e8b4ea3865897ce5144b99cd5 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 3 Jun 2020 06:22:49 -0400 Subject: [PATCH] verilator suppor for opae (partial) --- Makefile | 5 + driver/common/vx_utils.cpp | 2 +- driver/opae/Makefile | 2 +- driver/rtlsim/Makefile | 15 +- driver/rtlsim/ram.h | 64 +++++++ driver/rtlsim/simulator.cpp | 70 +++++++ driver/rtlsim/simulator.h | 59 ++++++ driver/rtlsim/vortex.cpp | 3 - driver/simx/Makefile | 2 +- driver/simx/vortex.cpp | 2 +- driver/tests/basic/Makefile | 1 + driver/tests/basic/common.h | 4 +- driver/tests/basic/kernel.bin | Bin 6548 -> 6556 bytes driver/tests/basic/kernel.c | 2 +- driver/tests/demo/Makefile | 1 + hw/Makefile | 93 +-------- hw/opae/ccip/ccip_if_pkg.sv | 238 ++++++++++++++++++++++++ hw/opae/ccip/local_mem_cfg_pkg.sv | 61 ++++++ hw/rtl/VX_dram_arb.v | 2 +- hw/rtl/Vortex.v | 1 - hw/rtl/Vortex_Cluster.v | 1 - hw/rtl/Vortex_Socket.v | 1 - hw/rtl/libs/VX_generic_queue.v | 2 +- hw/simulate/Makefile | 89 +++++++++ hw/simulate/simulator.cpp | 8 - hw/simulate/simulator.h | 2 +- runtime/Makefile | 4 +- runtime/fileio/fileio.S | 3 +- runtime/intrinsics/vx_intrinsics.S | 2 +- runtime/io/vx_io.S | 2 +- runtime/startup/vx_start.S | 2 +- runtime/tests/simple/Makefile | 2 + runtime/tests/simple/vx_simple_main.elf | Bin 257244 -> 257244 bytes runtime/vx_api/vx_api.c | 2 +- simX/simX.cpp | 2 +- 35 files changed, 621 insertions(+), 128 deletions(-) create mode 100644 Makefile create mode 100644 driver/rtlsim/ram.h create mode 100644 driver/rtlsim/simulator.cpp create mode 100644 driver/rtlsim/simulator.h create mode 100644 hw/opae/ccip/ccip_if_pkg.sv create mode 100644 hw/opae/ccip/local_mem_cfg_pkg.sv create mode 100644 hw/simulate/Makefile diff --git a/Makefile b/Makefile new file mode 100644 index 00000000..b4710000 --- /dev/null +++ b/Makefile @@ -0,0 +1,5 @@ +all: + $(MAKE) -C hw + $(MAKE) -C driver + $(MAKE) -C runtime + $(MAKE) -C simX \ No newline at end of file diff --git a/driver/common/vx_utils.cpp b/driver/common/vx_utils.cpp index c15e2b7c..d4fcf518 100644 --- a/driver/common/vx_utils.cpp +++ b/driver/common/vx_utils.cpp @@ -2,7 +2,7 @@ #include #include #include -#include +#include extern int vx_dev_caps(int caps_id) { switch (caps_id) { diff --git a/driver/opae/Makefile b/driver/opae/Makefile index e7705d30..367d8833 100644 --- a/driver/opae/Makefile +++ b/driver/opae/Makefile @@ -1,7 +1,7 @@ CXXFLAGS += -std=c++11 -O0 -g -Wall -Wextra -pedantic -Wfatal-errors -CXXFLAGS += -I../include -I/tools/opae/1.4.0/include -I../../runtime +CXXFLAGS += -I../include -I/tools/opae/1.4.0/include -I../../hw LDFLAGS += -L/tools/opae/1.4.0/lib diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 6627faba..f8758a44 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -19,6 +19,7 @@ DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG = 1 +AFU=1 CFLAGS += -fPIC @@ -27,6 +28,8 @@ CFLAGS += -DUSE_RTLSIM $(MULTICORE) LDFLAGS += -shared -pthread # LDFLAGS += -dynamiclib -pthread +TOP = Vortex_Socket + SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache @@ -48,14 +51,22 @@ else VL_FLAGS += -DNDEBUG endif +# AFU +ifdef AFU + TOP = vortex_afu_sim + VL_FLAGS += -DNOPAE + CFLAGS += -DNOPAE + RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip +endif + PROJECT = libvortex.so # PROJECT = libvortex.dylib all: $(PROJECT) $(PROJECT): $(SRCS) - verilator --exe --cc Vortex_Socket.v $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) - make -j -C obj_dir -f VVortex_Socket.mk + verilator --exe --cc $(TOP) $(RTL_INCLUDE) $(VL_FLAGS) $(SRCS) -CFLAGS '$(CFLAGS)' -LDFLAGS '$(LDFLAGS)' -o ../$(PROJECT) + make -j -C obj_dir -f V$(TOP).mk clean: rm -rf $(PROJECT) obj_dir diff --git a/driver/rtlsim/ram.h b/driver/rtlsim/ram.h new file mode 100644 index 00000000..53df7e0f --- /dev/null +++ b/driver/rtlsim/ram.h @@ -0,0 +1,64 @@ +#pragma once + +#include +#include + +class RAM { +private: + + mutable uint8_t *mem_[(1 << 12)]; + + uint8_t *get(uint32_t address) const { + uint32_t block_addr = address >> 20; + uint32_t block_offset = address & 0x000FFFFF; + if (mem_[block_addr] == NULL) { + mem_[block_addr] = new uint8_t[(1 << 20)]; + } + return mem_[block_addr] + block_offset; + } + +public: + + RAM() { + for (uint32_t i = 0; i < (1 << 12); i++) { + mem_[i] = NULL; + } + } + + ~RAM() { + this->clear(); + } + + size_t size() const { + return (1ull << 32); + } + + void clear() { + for (uint32_t i = 0; i < (1 << 12); i++) { + if (mem_[i]) { + delete mem_[i]; + mem_[i] = NULL; + } + } + } + + void read(uint32_t address, uint32_t length, uint8_t *data) const { + for (unsigned i = 0; i < length; i++) { + data[i] = *this->get(address + i); + } + } + + void write(uint32_t address, uint32_t length, const uint8_t *data) { + for (unsigned i = 0; i < length; i++) { + *this->get(address + i) = data[i]; + } + } + + uint8_t& operator[](uint32_t address) { + return *get(address); + } + + const uint8_t& operator[](uint32_t address) const { + return *get(address); + } +}; \ No newline at end of file diff --git a/driver/rtlsim/simulator.cpp b/driver/rtlsim/simulator.cpp new file mode 100644 index 00000000..a0b3ad5d --- /dev/null +++ b/driver/rtlsim/simulator.cpp @@ -0,0 +1,70 @@ +#include "simulator.h" +#include +#include +#include + +uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +Simulator::Simulator() { + // force random values for unitialized signals + const char* args[] = {"", "+verilator+rand+reset+2", "+verilator+seed+50"}; + Verilated::commandArgs(3, args); + + vortex_ = new Vvortex_afu_sim(); + +#ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + trace_ = new VerilatedVcdC; + vortex_->trace(trace_, 99); + trace_->open("trace.vcd"); +#endif +} + +Simulator::~Simulator() { +#ifdef VCD_OUTPUT + trace_->close(); +#endif + delete vortex_; +} + +void Simulator::reset() { +#ifndef NDEBUG + std::cout << timestamp << ": [sim] reset()" << std::endl; +#endif + vortex_->reset = 1; + this->step(); + vortex_->reset = 0; + + dram_rsp_vec_.clear(); +} + +void Simulator::step() { + vortex_->clk = 0; + this->eval(); + + vortex_->clk = 1; + this->eval(); + + avs_driver(); + ccip_driver(); +} + +void Simulator::eval() { + vortex_->eval(); +#ifdef VCD_OUTPUT + trace_->dump(timestamp); +#endif + ++timestamp; +} + +void Simulator::avs_driver() { + //-- +} + + void Simulator::ccip_driver() { + //-- + } \ No newline at end of file diff --git a/driver/rtlsim/simulator.h b/driver/rtlsim/simulator.h new file mode 100644 index 00000000..50d666d3 --- /dev/null +++ b/driver/rtlsim/simulator.h @@ -0,0 +1,59 @@ +#pragma once + +#include "Vvortex_afu_sim.h" +#include "Vvortex_afu_sim__Syms.h" +#include "verilated.h" + +#ifdef VCD_OUTPUT +#include +#endif + +#include +#include "ram.h" + +#include +#include + +#define ENABLE_DRAM_STALLS +#define DRAM_LATENCY 100 +#define DRAM_RQ_SIZE 16 +#define DRAM_STALLS_MODULO 16 + +typedef struct { + int cycles_left; + uint8_t *data; + unsigned tag; +} dram_req_t; + +class Simulator { +public: + + Simulator(); + virtual ~Simulator(); + + void reset(); + + void step(); + + int mmio_read(uint64_t addr, uint64_t* value); + + int mmio_write(uint64_t addr, uint64_t value); + +private: + + void eval(); + + void avs_driver(); + + void ccip_driver(); + + std::vector dram_rsp_vec_; + + RAM ram_; + Vvortex_afu_sim *vortex_; + + +#ifdef VCD_OUTPUT + VerilatedVcdC *trace_; +#endif +}; \ No newline at end of file diff --git a/driver/rtlsim/vortex.cpp b/driver/rtlsim/vortex.cpp index 95314f62..f751d4c2 100644 --- a/driver/rtlsim/vortex.cpp +++ b/driver/rtlsim/vortex.cpp @@ -7,7 +7,6 @@ #include #include -#include #include /////////////////////////////////////////////////////////////////////////////// @@ -60,7 +59,6 @@ class vx_device { public: vx_device() { mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); - simulator_.attach_ram(&ram_); } ~vx_device() { @@ -146,7 +144,6 @@ public: private: size_t mem_allocation_; - RAM ram_; Simulator simulator_; std::future future_; }; diff --git a/driver/simx/Makefile b/driver/simx/Makefile index 7a005dcd..3207787c 100644 --- a/driver/simx/Makefile +++ b/driver/simx/Makefile @@ -1,7 +1,7 @@ CFLAGS += -std=c++11 -O3 -Wall -Wextra -pedantic -Wfatal-errors #CFLAGS += -std=c++11 -g -O0 -Wall -Wextra -pedantic -Wfatal-errors -CFLAGS += -I../../include -I../../../simX/include -I../../../runtime +CFLAGS += -I../../include -I../../../simX/include -I../../../hw CFLAGS += -fPIC diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp index 6290c432..394e1db2 100644 --- a/driver/simx/vortex.cpp +++ b/driver/simx/vortex.cpp @@ -9,7 +9,7 @@ #include #include -#include +#include #define PAGE_SIZE 4096 diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile index 0d5ce581..8199c0dc 100644 --- a/driver/tests/basic/Makefile +++ b/driver/tests/basic/Makefile @@ -15,6 +15,7 @@ VX_API = $(VX_RT_PATH)/vx_api/vx_api.c VX_FIO = $(VX_RT_PATH)/fileio/fileio.S VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections +VX_CFLAGS += -I../../../hw VX_SRCS = kernel.c diff --git a/driver/tests/basic/common.h b/driver/tests/basic/common.h index 3fdb128c..69bd8c1c 100644 --- a/driver/tests/basic/common.h +++ b/driver/tests/basic/common.h @@ -1,8 +1,8 @@ #ifndef _COMMON_H_ #define _COMMON_H_ -#define DEV_MEM_SRC_ADDR 0x10000000 -#define DEV_MEM_DST_ADDR 0x20000000 +#define DEV_MEM_SRC_ADDR 0x10000040 +#define DEV_MEM_DST_ADDR 0x20000080 #define NUM_BLOCKS 64 #endif \ No newline at end of file diff --git a/driver/tests/basic/kernel.bin b/driver/tests/basic/kernel.bin index e08ac81c4ea77f265c0f5ad0318a14af3f3bf6a6..cdd3dcc0bde6f3935f75856eca286890f4fe5168 100755 GIT binary patch delta 285 zcmWlTF-yZh0EJ(!cR3;`Y0owmp%kNn;v$D+%_5F2Vo)4}jvZ9|0iH;Evz(xVP!Za? zN>JCfL_~1+Cpe~q2u^x^@c7{I4ev_c%Cl<*nAYaZ>Cz!-`cKFaPYdRw2?o&`jzoJn zl5Q_H*2^(i4J-v?^VX~6Ks|@T5e60EIDg@C5#i#w^;A(%Hetzd)YG>47>%Iv#AbB6A?b1|#LIe>a7k;73anapE>i!_S>rtaM!uw}>`LIA(?eU}L zxHK`ECuZ#Ivusy*?`E3>PG&l!Y806&Pc|=+-ft}SR^kRcB50O&$ZKgfgS~BYFb9>{ Su2rGT3A;)CiYn0KGSolM)=r`T delta 272 zcmbPZJjJ+vIx7Ri4wHfE z-ZMC8i34e2)>bK?I??wG4e~(Dkk8;CCd|nAUs+9%L0P2{sE$EUn1vNY3r%KcP}qEY zIg>H#7pCNZ4=m>F3{1xD&lx6*nKBr&FK1=g&dwk(u}7MdVRCyrgYu$n3==mfF}2EW zyduZQ))EF344eFeF-q1YOqkO%%$W111K1X&i44M#nhwbfoJ_(jE|c?_ltn=*I>9PX sWh6HrU|J(2vWEfaQXmMCU})F_#43^u4U-F5XKa=bYhY%{5M^ip0A5r{G5`Po diff --git a/driver/tests/basic/kernel.c b/driver/tests/basic/kernel.c index 9572bcab..96401c43 100644 --- a/driver/tests/basic/kernel.c +++ b/driver/tests/basic/kernel.c @@ -1,5 +1,5 @@ #include -#include "config.h" +#include #include "intrinsics/vx_intrinsics.h" #include "common.h" diff --git a/driver/tests/demo/Makefile b/driver/tests/demo/Makefile index 1d03d777..e100c2a3 100644 --- a/driver/tests/demo/Makefile +++ b/driver/tests/demo/Makefile @@ -14,6 +14,7 @@ VX_API = $(VX_RT_PATH)/vx_api/vx_api.c #VX_FIO = $(VX_RT_PATH)/fileio/fileio.S VX_CFLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,$(VX_RT_PATH)/startup/vx_link.ld -ffreestanding -nostartfiles -Wl,--gc-sections +VX_CFLAGS += -I../../../hw VX_SRCS = kernel.c diff --git a/hw/Makefile b/hw/Makefile index be559a68..4c5575a4 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -1,95 +1,4 @@ -all: build-s - -CF += -std=c++11 -fms-extensions - -VF += --language 1800-2009 --assert -Wall -Wpedantic -VF += -Wno-DECLFILENAME -VF += --x-initial unique - -VF += -exe $(SRCS) $(INCLUDE) - -#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 -#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 -MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 - -# control RTL debug print states -DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ - -DDBG_PRINT_CORE_DCACHE \ - -DDBG_PRINT_CACHE_BANK \ - -DDBG_PRINT_CACHE_SNP \ - -DDBG_PRINT_CACHE_MSRQ \ - -DDBG_PRINT_DRAM \ - -DDBG_PRINT_OPAE - -#DBG_PRINT=$(DBG_PRINT_FLAGS) - -INCLUDE = -I./rtl/ -I./rtl/libs -I./rtl/interfaces -I./rtl/pipe_regs -I./rtl/cache -I./rtl/simulate - -SRCS += ./simulate/testbench.cpp ./simulate/simulator.cpp - -DBG += -DVCD_OUTPUT $(DBG_PRINT) - -THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') - .PHONY: build_config build_config: - ./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./simulate/VX_config.h - -gen-s: build_config - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG' - -gen-sd: build_config - verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG) - -gen-st: build_config - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS) - -gen-m: build_config - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' - -gen-md: build_config - verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG) - -gen-mt: build_config - verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS) - -build-s: gen-s - (cd obj_dir && make -j -f VVortex_Socket.mk) - -build-sd: gen-sd - (cd obj_dir && make -j -f VVortex_Socket.mk) - -build-st: gen-st - (cd obj_dir && make -j -f VVortex_Socket.mk) - -build-m: gen-m - (cd obj_dir && make -j -f VVortex_Socket.mk) - -build-md: gen-md - (cd obj_dir && make -j -f VVortex_Socket.mk) - -build-mt: gen-mt - (cd obj_dir && make -j -f VVortex_Socket.mk) - -run: run-s -run-s: build-s - (cd obj_dir && ./VVortex_Socket) - -run-sd: build-sd - (cd obj_dir && ./VVortex_Socket) - -run-st: build-st - (cd obj_dir && ./VVortex_Socket) - -run-m: build-m - (cd obj_dir && ./VVortex_Socket) - -run-md: build-md - (cd obj_dir && ./VVortex_Socket) - -run-mt: build-mt - (cd obj_dir && ./VVortex_Socket) - -clean: - rm -rf obj_dir \ No newline at end of file + ./scripts/gen_config.py --outv ./rtl/VX_user_config.vh --outc ./VX_config.h \ No newline at end of file diff --git a/hw/opae/ccip/ccip_if_pkg.sv b/hw/opae/ccip/ccip_if_pkg.sv new file mode 100644 index 00000000..d300d154 --- /dev/null +++ b/hw/opae/ccip/ccip_if_pkg.sv @@ -0,0 +1,238 @@ +// Date: 02/2/2016 +// Compliant with CCI-P spec v0.71 +package ccip_if_pkg; + +//===================================================================== +// CCI-P interface defines +//===================================================================== +parameter CCIP_VERSION_NUMBER = 12'h071; + +parameter CCIP_CLADDR_WIDTH = 42; +parameter CCIP_CLDATA_WIDTH = 512; + +parameter CCIP_MMIOADDR_WIDTH = 16; +parameter CCIP_MMIODATA_WIDTH = 64; +parameter CCIP_TID_WIDTH = 9; + +parameter CCIP_MDATA_WIDTH = 16; + + +// Number of requests that can be accepted after almost full is asserted. +parameter CCIP_TX_ALMOST_FULL_THRESHOLD = 8; + +parameter CCIP_MMIO_RD_TIMEOUT = 512; + +parameter CCIP_SYNC_RESET_POLARITY=1; // Active High Reset + +// Base types +//---------------------------------------------------------------------- +typedef logic [CCIP_CLADDR_WIDTH-1:0] t_ccip_clAddr; +typedef logic [CCIP_CLDATA_WIDTH-1:0] t_ccip_clData; + + +typedef logic [CCIP_MMIOADDR_WIDTH-1:0] t_ccip_mmioAddr; +typedef logic [CCIP_MMIODATA_WIDTH-1:0] t_ccip_mmioData; +typedef logic [CCIP_TID_WIDTH-1:0] t_ccip_tid; + + +typedef logic [CCIP_MDATA_WIDTH-1:0] t_ccip_mdata; +typedef logic [1:0] t_ccip_clNum; +typedef logic [2:0] t_ccip_qwIdx; + + +// Request Type Encodings +//---------------------------------------------------------------------- +// Channel 0 +typedef enum logic [3:0] { + eREQ_RDLINE_I = 4'h0, // Memory Read with FPGA Cache Hint=Invalid + eREQ_RDLINE_S = 4'h1 // Memory Read with FPGA Cache Hint=Shared +} t_ccip_c0_req; + +// Channel 1 +typedef enum logic [3:0] { + eREQ_WRLINE_I = 4'h0, // Memory Write with FPGA Cache Hint=Invalid + eREQ_WRLINE_M = 4'h1, // Memory Write with FPGA Cache Hint=Modified + eREQ_WRPUSH_I = 4'h2, // Memory Write with DDIO Hint ** NOT SUPPORTED CURRENTLY ** + eREQ_WRFENCE = 4'h4, // Memory Write Fence +// eREQ_ATOMIC = 4'h5, // Atomic operation: Compare-Exchange for Memory Addr ** NOT SUPPORTED CURRENTELY ** + eREQ_INTR = 4'h6 // Interrupt the CPU ** NOT SUPPORTED CURRENTLY ** +} t_ccip_c1_req; + +// Response Type Encodings +//---------------------------------------------------------------------- +// Channel 0 +typedef enum logic [3:0] { + eRSP_RDLINE = 4'h0, // Memory Read + eRSP_UMSG = 4'h4 // UMsg received +// eRSP_ATOMIC = 4'h5 // Atomic Operation: Compare-Exchange for Memory Addr +} t_ccip_c0_rsp; + +// Channel 1 +typedef enum logic [3:0] { + eRSP_WRLINE = 4'h0, // Memory Write + eRSP_WRFENCE = 4'h4, // Memory Write Fence + eRSP_INTR = 4'h6 // Interrupt delivered to the CPU ** NOT SUPPORTED CURRENTLY ** +} t_ccip_c1_rsp; + +// +// Virtual Channel Select +//---------------------------------------------------------------------- +typedef enum logic [1:0] { + eVC_VA = 2'b00, + eVC_VL0 = 2'b01, + eVC_VH0 = 2'b10, + eVC_VH1 = 2'b11 +} t_ccip_vc; + +// Multi-CL Memory Request +//---------------------------------------------------------------------- +typedef enum logic [1:0] { + eCL_LEN_1 = 2'b00, + eCL_LEN_2 = 2'b01, + eCL_LEN_4 = 2'b11 +} t_ccip_clLen; + +// +// Structures for Request and Response headers +//---------------------------------------------------------------------- +typedef struct packed { + t_ccip_vc vc_sel; + logic [1:0] rsvd1; // reserved, drive 0 + t_ccip_clLen cl_len; + t_ccip_c0_req req_type; + logic [5:0] rsvd0; // reserved, drive 0 + t_ccip_clAddr address; + t_ccip_mdata mdata; +} t_ccip_c0_ReqMemHdr; +parameter CCIP_C0TX_HDR_WIDTH = $bits(t_ccip_c0_ReqMemHdr); + +typedef struct packed { + logic [5:0] rsvd2; + t_ccip_vc vc_sel; + logic sop; + logic rsvd1; // reserved, drive 0 + t_ccip_clLen cl_len; + t_ccip_c1_req req_type; + logic [5:0] rsvd0; // reserved, drive 0 + t_ccip_clAddr address; + t_ccip_mdata mdata; +} t_ccip_c1_ReqMemHdr; +parameter CCIP_C1TX_HDR_WIDTH = $bits(t_ccip_c1_ReqMemHdr); + +typedef struct packed { + logic [5:0] rsvd2; // reserved, drive 0 + t_ccip_vc vc_sel; + logic [3:0] rsvd1; // reserved, drive 0 + t_ccip_c1_req req_type; + logic [47:0] rsvd0; // reserved, drive 0 + t_ccip_mdata mdata; +}t_ccip_c1_ReqFenceHdr; + +typedef struct packed { + t_ccip_vc vc_used; + logic rsvd1; // reserved, don't care + logic hit_miss; + logic [1:0] rsvd0; // reserved, don't care + t_ccip_clNum cl_num; + t_ccip_c0_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c0_RspMemHdr; +parameter CCIP_C0RX_HDR_WIDTH = $bits(t_ccip_c0_RspMemHdr); + +typedef struct packed { + t_ccip_vc vc_used; + logic rsvd1; // reserved, don't care + logic hit_miss; + logic format; + logic rsvd0; // reserved, don't care + t_ccip_clNum cl_num; + t_ccip_c1_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c1_RspMemHdr; +parameter CCIP_C1RX_HDR_WIDTH = $bits(t_ccip_c1_RspMemHdr); + +typedef struct packed { + logic [7:0] rsvd0; // reserved, don't care + t_ccip_c1_rsp resp_type; + t_ccip_mdata mdata; +} t_ccip_c1_RspFenceHdr; + +// Alternate Channel 0 MMIO request from host : +// MMIO requests arrive on the same channel as read responses, sharing +// t_if_ccip_c0_Rx below. When either mmioRdValid or mmioWrValid is set +// the message is an MMIO request and should be processed by casting +// t_if_ccip_c0_Rx.hdr to t_ccip_c0_ReqMmioHdr. +typedef struct packed { + t_ccip_mmioAddr address; // 4B aligned Mmio address + logic [1:0] length; // 2'b00- 4B, 2'b01- 8B, 2'b10- 64B + logic rsvd; // reserved, don't care + t_ccip_tid tid; +} t_ccip_c0_ReqMmioHdr; + +typedef struct packed { + t_ccip_tid tid; // Returned back from ReqMmioHdr +} t_ccip_c2_RspMmioHdr; +parameter CCIP_C2TX_HDR_WIDTH = $bits(t_ccip_c2_RspMmioHdr); + +//------------------------------------------------------------------------ +// CCI-P Input & Output bus structures +// +// Users are encouraged to use these for AFU development +//------------------------------------------------------------------------ +// Channel 0 : Memory Reads +typedef struct packed { + t_ccip_c0_ReqMemHdr hdr; // Request Header + logic valid; // Request Valid +} t_if_ccip_c0_Tx; + + +// Channel 1 : Memory Writes, Interrupts, CmpXchg +typedef struct packed { + t_ccip_c1_ReqMemHdr hdr; // Request Header + t_ccip_clData data; // Request Data + logic valid; // Request Wr Valid +} t_if_ccip_c1_Tx; + +// Channel 2 : MMIO Read response +typedef struct packed { + t_ccip_c2_RspMmioHdr hdr; // Response Header + logic mmioRdValid; // Response Read Valid + t_ccip_mmioData data; // Response Data +} t_if_ccip_c2_Tx; + +// Wrap all Tx channels +typedef struct packed { + t_if_ccip_c0_Tx c0; + t_if_ccip_c1_Tx c1; + t_if_ccip_c2_Tx c2; +} t_if_ccip_Tx; + +// Channel 0: Memory Read response, MMIO Request +typedef struct packed { + t_ccip_c0_RspMemHdr hdr; // Rd Response/ MMIO req Header + t_ccip_clData data; // Rd Data / MMIO req Data + // Only one of valid, mmioRdValid and mmioWrValid may be set + // in a cycle. When either mmioRdValid or mmioWrValid are true + // the hdr must be processed specially. See t_ccip_c0_ReqMmioHdr + // above. + logic rspValid; // Rd Response Valid + logic mmioRdValid; // MMIO Read Valid + logic mmioWrValid; // MMIO Write Valid +} t_if_ccip_c0_Rx; + +// Channel 1: Memory Writes +typedef struct packed { + t_ccip_c1_RspMemHdr hdr; // Response Header + logic rspValid; // Response Valid +} t_if_ccip_c1_Rx; + +// Wrap all channels +typedef struct packed { + logic c0TxAlmFull; // C0 Request Channel Almost Full + logic c1TxAlmFull; // C1 Request Channel Almost Full + + t_if_ccip_c0_Rx c0; + t_if_ccip_c1_Rx c1; +} t_if_ccip_Rx; + +endpackage \ No newline at end of file diff --git a/hw/opae/ccip/local_mem_cfg_pkg.sv b/hw/opae/ccip/local_mem_cfg_pkg.sv new file mode 100644 index 00000000..97205e3c --- /dev/null +++ b/hw/opae/ccip/local_mem_cfg_pkg.sv @@ -0,0 +1,61 @@ +// +// Copyright (c) 2017, Intel Corporation +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, this +// list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the Intel Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. + +//`include "platform_afu_top_config.vh" + +`ifdef PLATFORM_PROVIDES_LOCAL_MEMORY + +package local_mem_cfg_pkg; + + parameter LOCAL_MEM_VERSION_NUMBER = 1; + + parameter LOCAL_MEM_ADDR_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH; + parameter LOCAL_MEM_DATA_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH; + + parameter LOCAL_MEM_BURST_CNT_WIDTH = `PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH; + + // Number of bytes in a data line + parameter LOCAL_MEM_DATA_N_BYTES = LOCAL_MEM_DATA_WIDTH / 8; + + + // Base types + // -------------------------------------------------------------------- + + typedef logic [LOCAL_MEM_ADDR_WIDTH-1:0] t_local_mem_addr; + typedef logic [LOCAL_MEM_DATA_WIDTH-1:0] t_local_mem_data; + + typedef logic [LOCAL_MEM_BURST_CNT_WIDTH-1:0] t_local_mem_burst_cnt; + + // Byte-level mask of a data line + typedef logic [LOCAL_MEM_DATA_N_BYTES-1:0] t_local_mem_byte_mask; + +endpackage // local_mem_cfg_pkg + +`endif // PLATFORM_PROVIDES_LOCAL_MEMORY \ No newline at end of file diff --git a/hw/rtl/VX_dram_arb.v b/hw/rtl/VX_dram_arb.v index b5e7a605..6d91a959 100644 --- a/hw/rtl/VX_dram_arb.v +++ b/hw/rtl/VX_dram_arb.v @@ -1,4 +1,4 @@ -`include "VX_cache_config.vh" +`include "VX_define.vh" module VX_dram_arb #( parameter BANK_LINE_SIZE = 1, diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 6861eca8..4ff18438 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -1,5 +1,4 @@ `include "VX_define.vh" -`include "VX_cache_config.vh" module Vortex #( parameter CORE_ID = 0 diff --git a/hw/rtl/Vortex_Cluster.v b/hw/rtl/Vortex_Cluster.v index f90082dd..cafb47a1 100644 --- a/hw/rtl/Vortex_Cluster.v +++ b/hw/rtl/Vortex_Cluster.v @@ -1,5 +1,4 @@ `include "VX_define.vh" -`include "VX_cache_config.vh" module Vortex_Cluster #( parameter CLUSTER_ID = 0 diff --git a/hw/rtl/Vortex_Socket.v b/hw/rtl/Vortex_Socket.v index 78382a5e..a225b0f9 100644 --- a/hw/rtl/Vortex_Socket.v +++ b/hw/rtl/Vortex_Socket.v @@ -1,5 +1,4 @@ `include "VX_define.vh" -`include "VX_cache_config.vh" module Vortex_Socket ( // Clock diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 40f130bb..b196d48c 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -132,7 +132,7 @@ module VX_generic_queue #( wr_ptr_r <= wr_ptr_r + 1; if (!reading) begin empty_r <= 0; - if (size_r == SIZE-1) begin + if (size_r == $bits(size_r)'(SIZE-1)) begin full_r <= 1; end size_r <= size_r + 1; diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile new file mode 100644 index 00000000..b66b082b --- /dev/null +++ b/hw/simulate/Makefile @@ -0,0 +1,89 @@ +#MULTICORE += -DNUM_CLUSTERS=2 -DNUM_CORES=4 +#MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=4 +MULTICORE += -DNUM_CLUSTERS=1 -DNUM_CORES=2 + +# control RTL debug print states +DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ + -DDBG_PRINT_CORE_DCACHE \ + -DDBG_PRINT_CACHE_BANK \ + -DDBG_PRINT_CACHE_SNP \ + -DDBG_PRINT_CACHE_MSRQ \ + -DDBG_PRINT_DRAM \ + -DDBG_PRINT_OPAE + +#DBG_PRINT=$(DBG_PRINT_FLAGS) + +INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate + +SRCS = simulator.cpp testbench.cpp + +all: build-s + +CF += -std=c++11 -fms-extensions -I../.. + +VF += --language 1800-2009 --assert -Wall -Wpedantic +VF += -Wno-DECLFILENAME +VF += --x-initial unique +VF += -exe $(SRCS) $(INCLUDE) + +DBG += -DVCD_OUTPUT $(DBG_PRINT) + +THREADS ?= $(shell python3 -c 'import multiprocessing as mp; print(max(1, mp.cpu_count() // 2))') + +gen-s: + verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG' + +gen-sd: + verilator $(VF) -cc Vortex_Socket.v -CFLAGS '$(CF) -g -O0 $(DBG)' --trace $(DBG) + +gen-st: + verilator $(VF) -DNDEBUG -cc Vortex_Socket.v -CFLAGS '$(CF) -DNDEBUG -O2' --threads $(THREADS) + +gen-m: + verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG $(MULTICORE)' + +gen-md: + verilator $(VF) -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -g -O0 $(DBG) $(MULTICORE)' --trace $(DBG) + +gen-mt: + verilator $(VF) -DNDEBUG -cc Vortex_Socket.v $(MULTICORE) -CFLAGS '$(CF) -DNDEBUG -O2 $(MULTICORE)' --threads $(THREADS) + +build-s: gen-s + (cd obj_dir && make -j -f VVortex_Socket.mk) + +build-sd: gen-sd + (cd obj_dir && make -j -f VVortex_Socket.mk) + +build-st: gen-st + (cd obj_dir && make -j -f VVortex_Socket.mk) + +build-m: gen-m + (cd obj_dir && make -j -f VVortex_Socket.mk) + +build-md: gen-md + (cd obj_dir && make -j -f VVortex_Socket.mk) + +build-mt: gen-mt + (cd obj_dir && make -j -f VVortex_Socket.mk) + +run: run-s +run-s: build-s + (cd obj_dir && ./VVortex_Socket) + +run-sd: build-sd + (cd obj_dir && ./VVortex_Socket) + +run-st: build-st + (cd obj_dir && ./VVortex_Socket) + +run-m: build-m + (cd obj_dir && ./VVortex_Socket) + +run-md: build-md + (cd obj_dir && ./VVortex_Socket) + +run-mt: build-mt + (cd obj_dir && ./VVortex_Socket) + +clean: + rm -rf obj_dir \ No newline at end of file diff --git a/hw/simulate/simulator.cpp b/hw/simulate/simulator.cpp index f8314a34..8ffdf7ef 100644 --- a/hw/simulate/simulator.cpp +++ b/hw/simulate/simulator.cpp @@ -17,14 +17,6 @@ Simulator::Simulator() { ram_ = nullptr; vortex_ = new VVortex_Socket(); - // initial values - vortex_->dram_req_ready = 0; - vortex_->dram_rsp_valid = 0; - vortex_->io_req_ready = 0; - vortex_->io_rsp_valid = 0; - vortex_->snp_req_valid = 0; - vortex_->snp_rsp_ready = 0; - #ifdef VCD_OUTPUT Verilated::traceEverOn(true); trace_ = new VerilatedVcdC; diff --git a/hw/simulate/simulator.h b/hw/simulate/simulator.h index 87c3406c..d68ae04d 100644 --- a/hw/simulate/simulator.h +++ b/hw/simulate/simulator.h @@ -8,7 +8,7 @@ #include #endif -#include "VX_config.h" +#include #include "ram.h" #include diff --git a/runtime/Makefile b/runtime/Makefile index b66181b9..1d1f1a83 100644 --- a/runtime/Makefile +++ b/runtime/Makefile @@ -1,6 +1,4 @@ -.PHONY: build_config -build_config: - ../hw/scripts/gen_config.py --outv none --outc ./config.h +all: diff --git a/runtime/fileio/fileio.S b/runtime/fileio/fileio.S index c7086e01..0e9c5b67 100644 --- a/runtime/fileio/fileio.S +++ b/runtime/fileio/fileio.S @@ -1,5 +1,4 @@ - -#include "../config.h" +#include # .section .FileIO diff --git a/runtime/intrinsics/vx_intrinsics.S b/runtime/intrinsics/vx_intrinsics.S index 3e09b4b7..b0dbd628 100644 --- a/runtime/intrinsics/vx_intrinsics.S +++ b/runtime/intrinsics/vx_intrinsics.S @@ -1,4 +1,4 @@ -#include "../config.h" +#include .section .text diff --git a/runtime/io/vx_io.S b/runtime/io/vx_io.S index f01222c0..60d0897d 100644 --- a/runtime/io/vx_io.S +++ b/runtime/io/vx_io.S @@ -1,4 +1,4 @@ -#include "../config.h" +#include .type vx_print_str, @function .global vx_print_str diff --git a/runtime/startup/vx_start.S b/runtime/startup/vx_start.S index 7d5190fe..029fbb90 100644 --- a/runtime/startup/vx_start.S +++ b/runtime/startup/vx_start.S @@ -1,4 +1,4 @@ -#include "../config.h" +#include .section .init, "ax" .global _start diff --git a/runtime/tests/simple/Makefile b/runtime/tests/simple/Makefile index 844bfa8a..9edbb0f2 100644 --- a/runtime/tests/simple/Makefile +++ b/runtime/tests/simple/Makefile @@ -4,6 +4,8 @@ COMP = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-g++ CC_FLAGS = -march=rv32im -mabi=ilp32 -O3 -Wl,-Bstatic,-T,../../startup/vx_link.ld CC_FLAGS += -nostartfiles -ffreestanding -fno-rtti -fno-exceptions -Wl,--gc-sections +CC_FLAGS += -I../../../hw + DMP = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objdump CPY = ~/dev/riscv-gnu-toolchain/drops/bin/riscv32-unknown-elf-objcopy diff --git a/runtime/tests/simple/vx_simple_main.elf b/runtime/tests/simple/vx_simple_main.elf index 08d3e59d32b2229113de2aa7eaed70d22fe72b3c..07e759ff6ae8f190c09fbb2a2fb328938b426dfd 100755 GIT binary patch delta 40 wcmca}lmE_5{)QID7N#xCKDXHX!irtOU8e`#VoqmEHmu01^4z}v7PG7n09yeM+yDRo delta 40 wcmca}lmE_5{)QID7N#xCKDXG6Go9QVEv5(EVoqnP3JNhbkJ`Tf7PG7n08tDNF8}}l diff --git a/runtime/vx_api/vx_api.c b/runtime/vx_api/vx_api.c index 27930c85..1019346d 100644 --- a/runtime/vx_api/vx_api.c +++ b/runtime/vx_api/vx_api.c @@ -1,4 +1,4 @@ -#include "../config.h" +#include #include "../intrinsics/vx_intrinsics.h" #include "vx_api.h" #include diff --git a/simX/simX.cpp b/simX/simX.cpp index 46e836b9..a67ed075 100644 --- a/simX/simX.cpp +++ b/simX/simX.cpp @@ -21,7 +21,7 @@ #include "include/args.h" #include "include/help.h" -#include "../runtime/config.h" +#include #include