register file refactoring

2020-12-05 01:40:50 -08:00
parent 478d971389
commit 13a5370254
33 changed files with 524 additions and 605 deletions
--- a/hw/rtl/libs/VX_stream_arbiter.v
+++ b/hw/rtl/libs/VX_stream_arbiter.v
@@ -106,12 +106,12 @@ module VX_stream_arbiter #(
                .N(1 + DATAW),
                .R(1)
            ) pipe_reg (
-                .clk   (clk),
-                .reset (reset),
-                .stall (stall),
-                .flush (1'b0),
-                .in    ({sel_valid, data_in[sel_idx]}),
-                .out   ({valid_out, data_out})
+                .clk      (clk),
+                .reset    (reset),
+                .stall    (stall),
+                .flush    (1'b0),
+                .data_in  ({sel_valid, data_in[sel_idx]}),
+                .data_out ({valid_out, data_out})
            );

            for (genvar i = 0; i < NUM_REQS; i++) begin