minor update

.gitignore

@@ -1,9 +0,0 @@
-./rtl/obj_dir/
-./rtl/obj_dir/*.vcd
-./rtl/.*
-./rtl/modelsim/*.vcd
-*.vcd
-.*
-!.gitignore
-*.pyc
-__pycache__

hw/opae/Makefile

@@ -2,7 +2,7 @@
 ASE_BUILD_DIR=build_ase
 FPGA_BUILD_DIR=build_fpga
 
-all: ase fpga fpga-1c
+all: ase ase-1c fpga fpga-1c
 
 ase: setup-ase
 	make -C $(ASE_BUILD_DIR)
@@ -12,6 +12,14 @@ setup-ase: $(ASE_BUILD_DIR)/Makefile
 $(ASE_BUILD_DIR)/Makefile:
 	afu_sim_setup -s sources.txt $(ASE_BUILD_DIR)
 
+ase-1c: setup-ase-1c
+	make -C $(ASE_BUILD_DIR)_1c
+
+setup-ase-1c: $(ASE_BUILD_DIR)_1c/Makefile
+
+$(ASE_BUILD_DIR)_1c/Makefile:
+	afu_sim_setup -s sources_1c.txt $(ASE_BUILD_DIR)_1c
+
 fpga: setup-fpga
 	cd $(FPGA_BUILD_DIR) && qsub-synth
 
@@ -31,6 +39,9 @@ $(FPGA_BUILD_DIR)_1c/build/dcp.qpf:
 run-ase:
 	cd $(ASE_BUILD_DIR) && make sim
 
+run-ase-1c:
+	cd $(ASE_BUILD_DIR)_1c && make sim
+
 wave:
 	vsim -view $(ASE_BUILD_DIR)/work/vsim.wlf -do wave.do
 
@@ -40,5 +51,11 @@ run-fpga:
 clean-ase:
 	rm -rf $(ASE_BUILD_DIR)
 
+clean-ase-1c:
+	rm -rf $(ASE_BUILD_DIR)_1c
+
 clean-fpga:
-	rm -rf $(FPGA_BUILD_DIR)
+	rm -rf $(FPGA_BUILD_DIR)
+
+clean-fpga-1c:
+	rm -rf $(FPGA_BUILD_DIR)_1c

hw/opae/README

@@ -58,8 +58,8 @@ source /export/fpga/bin/setup-fpga-env fpga-pac-a10
 qsub-sim
 
 # tests
-./run_ase.sh ../../driver/tests/basic/basic
+./run_ase.sh build_ase ../../driver/tests/basic/basic
-./run_ase.sh ../../driver/tests/demo/demo
+./run_ase.sh build_ase ../../driver/tests/demo/demo
 
 # modify "vsim_run.tcl" to dump VCD trace
 vcd file vortex.vcd

hw/opae/run_ase.sh

@@ -1,22 +1,25 @@
 #!/bin/bash
 
 SCRIPT_DIR=$PWD
-PROGRAM=$(basename "$1")
+
-PROGRAM_DIR=`dirname $1`
+BUILD_DIR=$1
+
+PROGRAM=$(basename "$2")
+PROGRAM_DIR=`dirname $2`
 
 # Export ASE_WORKDIR variable
-export ASE_WORKDIR=$SCRIPT_DIR/build_ase/work
+export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work
 
-shift 1
+shift 2
 
 # cleanup incomplete runs
 rm -f $ASE_WORKDIR/.app_lock.pid 
 rm -f $ASE_WORKDIR/.ase_ready.pid
-rm -f $SCRIPT_DIR/build_ase/nohup.out
+rm -f $SCRIPT_DIR/$BUILD_DIR/nohup.out
 
 # Start Simulator in background
-pushd $SCRIPT_DIR/build_ase 
+pushd $SCRIPT_DIR/$BUILD_DIR 
-echo "  [DBG]  starting ASE simnulator (stdout saved to '$SCRIPT_DIR/build_ase/nohup.out')"
+echo "  [DBG]  starting ASE simnulator (stdout saved to '$SCRIPT_DIR/$BUILD_DIR/nohup.out')"
 nohup make sim & 
 popd
 

hw/opae/sources.txt

@@ -2,7 +2,21 @@ vortex_afu.json
 
 +define+GLOBAL_BLOCK_SIZE=64
 
++define+DCACHE_SIZE=2048
++define+ICACHE_SIZE=1024
++define+SCACHE_SIZE=1024
+
 +define+NUM_CORES=2
++define+NUM_WARPS=4
++define+NUM_THREADS=4
+
++define+DNUM_BANKS=4
++define+INUM_BANKS=2
++define+SNUM_BANKS=4
+
++define+DDFPQ_SIZE=16
++define+IDFPQ_SIZE=16
++define+SDFPQ_SIZE=0
 
 #+define+DBG_PRINT_CORE_ICACHE
 #+define+DBG_PRINT_CORE_DCACHE

hw/syn/quartus/scheduler/Makefile

@@ -1,70 +0,0 @@
-PROJECT = VX_scheduler
-TOP_LEVEL_ENTITY = VX_scheduler
-SRC_FILE = VX_scheduler.v
-PROJECT_FILES = $(PROJECT).qpf $(PROJECT).qsf
-
-# Part, Family
-FAMILY = "Arria 10"
-DEVICE = 10AX115N3F40E2SG   
-
-# Executable Configuration
-SYN_ARGS = --parallel --read_settings_files=on
-FIT_ARGS = --part=$(DEVICE) --read_settings_files=on
-ASM_ARGS =
-STA_ARGS = --do_report_timing
-
-# Build targets
-all: $(PROJECT).sta.rpt
-
-syn: $(PROJECT).syn.rpt
-
-fit: $(PROJECT).fit.rpt
-
-asm: $(PROJECT).asm.rpt
-
-sta: $(PROJECT).sta.rpt
-
-smart: smart.log
-
-# Target implementations
-STAMP = echo done >
-
-$(PROJECT).syn.rpt: smart.log syn.chg $(SOURCE_FILES) 
-	quartus_syn $(PROJECT) $(SYN_ARGS)
-	$(STAMP) fit.chg
-
-$(PROJECT).fit.rpt: smart.log fit.chg $(PROJECT).syn.rpt
-	quartus_fit $(PROJECT) $(FIT_ARGS)
-	$(STAMP) asm.chg
-	$(STAMP) sta.chg
-
-$(PROJECT).asm.rpt: smart.log asm.chg $(PROJECT).fit.rpt
-	quartus_asm $(PROJECT) $(ASM_ARGS)
-
-$(PROJECT).sta.rpt: smart.log sta.chg $(PROJECT).fit.rpt
-	quartus_sta $(PROJECT)  $(STA_ARGS) 
-
-smart.log: $(PROJECT_FILES)
-	quartus_sh --determine_smart_action $(PROJECT) > smart.log
-
-# Project initialization
-$(PROJECT_FILES):
-	quartus_sh -t project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache"
-	
-syn.chg:
-	$(STAMP) syn.chg
-
-fit.chg:
-	$(STAMP) fit.chg
-
-sta.chg:
-	$(STAMP) sta.chg
-
-asm.chg:
-	$(STAMP) asm.chg
-
-program: $(PROJECT).sof
-	quartus_pgm --no_banner --mode=jtag -o "$(PROJECT).sof"
-	
-clean:
-	rm -rf bin *.rpt *.chg *.qsf *.qpf *.qws smart.log *.htm *.eqn *.pin *.sof *.pof qdb incremental_db tmp-clearbox

hw/syn/quartus/scheduler/project.sdc

@@ -1 +0,0 @@
-create_clock -name {clk} -period "250 MHz" -waveform { 0.0 1.0 } [get_ports {clk}]

hw/syn/quartus/scheduler/project.tcl

@@ -1,41 +0,0 @@
-load_package flow
-package require cmdline
-
-set options { \
-    { "project.arg" "" "Project name" } \
-    { "family.arg" "" "Device family name" } \
-    { "device.arg" "" "Device name" } \
-    { "top.arg" "" "Top level module" } \
-    { "sdc.arg" "" "Timing Design Constraints file" } \
-    { "src.arg" "" "Verilog source file" } \
-    { "inc.arg" "." "Include path" } \
-}
-
-array set opts [::cmdline::getoptions quartus(args) $options]
-
-project_new $opts(project) -overwrite
-
-set_global_assignment -name FAMILY $opts(family)
-set_global_assignment -name DEVICE $opts(device)
-set_global_assignment -name TOP_LEVEL_ENTITY $opts(top)
-set_global_assignment -name VERILOG_FILE $opts(src)
-set_global_assignment -name SEARCH_PATH $opts(inc)
-set_global_assignment -name SDC_FILE $opts(sdc)
-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY bin
-set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
-set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009
-
-proc make_all_pins_virtual {} {
-    execute_module -tool map
-    set name_ids [get_names -filter * -node_type pin]
-    foreach_in_collection name_id $name_ids {        
-        set pin_name [get_name_info -info full_path $name_id]
-        post_message "Making VIRTUAL_PIN assignment to $pin_name"
-        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
-    }
-    export_assignments
-}
-
-make_all_pins_virtual
-
-project_close